Articles liés à Loop Tiling for Parallelism
Synopsis
Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines.
Features and key topics:
- Detailed review of the mathematical foundations, including convex polyhedra and cones;
- Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability;
- Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation;
- A complete suite of techniques for generating SPMD code for a tiled loop nest;
- Up-to-date results on tile size and shape selection for reducing communication and improving parallelism;
- End-of-chapter references for further reading.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
Acheter neuf
Afficher cet article
EUR 136,16
EUR 9,70 expédition depuis Allemagne vers France
Destinations, frais et délaisAutres éditions populaires du même titre
Résultats de recherche pour Loop Tiling for Parallelism
Image d'archives
Loop Tiling for Parallelism (The Springer International Series in Engineering and Computer Science)
Edité par
Springer, 2000
ISBN 10 : 0792379330
ISBN 13 : 9780792379331
Ancien ou d'occasion
Couverture rigide
Vendeur : Westland Books, Wymondham, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Good. UK stocked, available immediately. Hardcover, published by Kluwer Academic Publishers in 2000. A withdrawn library copy with stamps and markings. The text is unmarked throughout, a good usable copy. Illustrated. Weight (unpacked) is 580 grams. N° de réf. du vendeur st9xasd580
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
Loop Tiling for Parallelism
impression à la demandeVendeur : moluna, Greven, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Gebunden. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for. N° de réf. du vendeur 5970542
Quantité disponible : Plus de 20 disponibles
Image d'archives
Loop Tiling for Parallelism (The Springer International Series in Engineering and Computer Science, 575)
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. In. N° de réf. du vendeur ria9780792379331_new
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Loop Tiling for Parallelism
Edité par
Springer US Aug 2000, 2000
ISBN 10 : 0792379330
ISBN 13 : 9780792379331
Neuf
Couverture rigide
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines. Features and key topics: Detailed review of the mathematical foundations, including convex polyhedra and cones; Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability; Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation; A complete suite of techniques for generating SPMD code for a tiled loop nest; Up-to-date results on tile size and shape selection for reducing communication and improving parallelism; End-of-chapter references for further reading. Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources. 280 pp. Englisch. N° de réf. du vendeur 9780792379331
Quantité disponible : 2 disponible(s)
Image fournie par le vendeur
Loop Tiling for Parallelism
Edité par
Springer US, Springer New York Aug 2000, 2000
ISBN 10 : 0792379330
ISBN 13 : 9780792379331
Neuf
Couverture rigide
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Buch. Etat : Neu. Neuware -Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines.Features and key topics: Detailed review of the mathematical foundations, including convex polyhedra and cones;Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability;Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation;A complete suite of techniques for generating SPMD code for a tiled loop nest;Up-to-date results on tile size and shape selection for reducing communication and improving parallelism;End-of-chapter references for further reading.Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 280 pp. Englisch. N° de réf. du vendeur 9780792379331
Quantité disponible : 2 disponible(s)
Image fournie par le vendeur
Loop Tiling for Parallelism
Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur 757349-n
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Loop Tiling for Parallelism
Edité par
Springer US, Springer New York, 2000
ISBN 10 : 0792379330
ISBN 13 : 9780792379331
Neuf
Couverture rigide
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Buch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines. Features and key topics: Detailed review of the mathematical foundations, including convex polyhedra and cones; Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability; Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation; A complete suite of techniques for generating SPMD code for a tiled loop nest; Up-to-date results on tile size and shape selection for reducing communication and improving parallelism; End-of-chapter references for further reading. Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources. N° de réf. du vendeur 9780792379331
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
Loop Tiling for Parallelism
Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur 757349-n
Quantité disponible : Plus de 20 disponibles
Image d'archives
Loop Tiling for Parallelism (The Springer International Series in Engineering and Computer Science, 575)
Vendeur : BennettBooksLtd, North Las Vegas, NV, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Hardcover. Etat : New. In shrink wrap. Looks like an interesting title! N° de réf. du vendeur Q-0792379330
Quantité disponible : 1 disponible(s)
Image d'archives
Loop Tiling for Parallelism (The Springer International Series in Engineering and Computer Science, 575)
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur ABLIING23Feb2416190184886
Quantité disponible : Plus de 20 disponibles