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Destinations, frais et délaisVendeur : HPB-Red, Dallas, TX, Etats-Unis
Hardcover. Etat : Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority! N° de réf. du vendeur S_326135952
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Vendeur : Goodwill of Silicon Valley, SAN JOSE, CA, Etats-Unis
Etat : good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear. N° de réf. du vendeur GWSVV.0792395131.G
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Vendeur : Kellogg Creek Books, Portland, OR, Etats-Unis
Hardcover. Etat : Fine. Binding tight, content clean and straight. Appears unread. Cover in excellent, shiny condition. If purchasing internationally, inquire about shipping charges before purchase. Ships within 1-2 business days. N° de réf. du vendeur 2646
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Vendeur : Librairie Parrêsia, Figeac, France
Hardcover. Etat : Used: Good. Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power | J. van de Plassche et alii | Kluwer Academic, 1995, in-8 cartonnage éditeur, 400 pages. Couverture propre. Dos solide. Intérieur frais. Exemplaire de bibliothèque : petit code barre en pied de 1re de couv., cotation au dos, rares et discrets petits tampons à l'intérieur de l'ouvrage. Bel état ! [BT35]. N° de réf. du vendeur 0705UN578BS
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Vendeur : Buchpark, Trebbin, Allemagne
Etat : Sehr gut. Zustand: Sehr gut - Gepflegter, sauberer Zustand. Außen: verschmutzt, angestoßen. Aus der Auflösung einer renommierten Bibliothek. Kann Stempel beinhalten. | Seiten: 412 | Sprache: Englisch | Produktart: Bücher. N° de réf. du vendeur 3011933/202
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Gebunden. Etat : New. N° de réf. du vendeur 5971551
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Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of 'analog clock cycles' required to produce one effective output sample of the signal being quantized. 412 pp. Englisch. N° de réf. du vendeur 9780792395133
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Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Etat : New. In. N° de réf. du vendeur ria9780792395133_new
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Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Buch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of 'analog clock cycles' required to produce one effective output sample of the signal being quantized. N° de réf. du vendeur 9780792395133
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