The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ- ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif- ferent conversion techniques applicable in this range of sample rates is dis- cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi- zation of capacitor sizes, design of low-voltage transmission gates, and opti- mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech- niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of "analog clock cycles" required to produce one effective output sample of the signal being quantized.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
Vendeur : Kellogg Creek Books, Portland, OR, Etats-Unis
Hardcover. Etat : Fine. Binding tight, content clean and straight. Appears unread. Cover in excellent, shiny condition. If purchasing internationally, inquire about shipping charges before purchase. Ships within 1-2 business days. N° de réf. du vendeur 2646
Quantité disponible : 1 disponible(s)
Vendeur : Librairie Parrêsia, Figeac, France
Hardcover Nov 30, 1994. Etat : Used: Good. Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power | J. van de Plassche et alii | Kluwer Academic, 1995, in-8 cartonnage éditeur, 400 pages. Couverture propre. Dos solide. Intérieur frais. Exemplaire de bibliothèque : petit code barre en pied de 1re de couv., cotation au dos, rares et discrets petits tampons à l'intérieur de l'ouvrage. Bel état ! [BT35]. N° de réf. du vendeur 0705UN578BS
Quantité disponible : 1 disponible(s)
Vendeur : HPB-Red, Dallas, TX, Etats-Unis
Hardcover. Etat : Acceptable. Connecting readers with great books since 1972. Used textbooks may not include companion materials such as access codes, etc. May have condition issues including wear and notes/highlighting. We ship orders daily and Customer Service is our top priority! N° de réf. du vendeur S_467516975
Quantité disponible : 1 disponible(s)
Vendeur : HPB-Red, Dallas, TX, Etats-Unis
Hardcover. Etat : Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority! N° de réf. du vendeur S_381177562
Quantité disponible : 1 disponible(s)
Vendeur : Phatpocket Limited, Waltham Abbey, HERTS, Royaume-Uni
Etat : Good. Your purchase helps support Sri Lankan Children's Charity 'The Rainbow Centre'. Ex-library, so some stamps and wear, but in good overall condition. Our donations to The Rainbow Centre have helped provide an education and a safe haven to hundreds of children who live in appalling conditions. N° de réf. du vendeur Z1-W-020-02637
Quantité disponible : 1 disponible(s)
Vendeur : moluna, Greven, Allemagne
Gebunden. Etat : New. N° de réf. du vendeur 5971551
Quantité disponible : Plus de 20 disponibles
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of 'analog clock cycles' required to produce one effective output sample of the signal being quantized. 412 pp. Englisch. N° de réf. du vendeur 9780792395133
Quantité disponible : 2 disponible(s)
Vendeur : preigu, Osnabrück, Allemagne
Buch. Etat : Neu. Analog Circuit Design | Low-Power Low-Voltage, Integrated Filters and Smart Power | Rudy J. Van De Plassche (u. a.) | Buch | viii | Englisch | 1994 | Springer US | EAN 9780792395133 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. N° de réf. du vendeur 102548887
Quantité disponible : 5 disponible(s)
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Etat : New. In English. N° de réf. du vendeur ria9780792395133_new
Quantité disponible : Plus de 20 disponibles
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Buch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The realization of signal sampling and quantization at high sample rates with low power dissipation is an important goal in many applications, includ ing portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, in the read channels of magnetic storage devices using digital data detection, and many others. This paper describes architecture and circuit approaches for the design of high-speed, low-power pipeline analog-to-digital converters in CMOS. Here the term high speed is taken to imply sampling rates above 1 Mhz. In the first section the dif ferent conversion techniques applicable in this range of sample rates is dis cussed. Following that the particular problems associated with power minimization in video-rate pipeline ADCs is discussed. These include optimi zation of capacitor sizes, design of low-voltage transmission gates, and opti mization of switched capacitor gain blocks and operational amplifiers for minimum power dissipation. As an example of the application of these tech niques, the design of a power-optimized lO-bit pipeline AID converter (ADC) that achieves =1. 67 mW per MS/s of sampling rate from 1 MS/s to 20 MS/s is described. 2. Techniques for CMOS Video-Rate AID Conversion Analog-to-digital conversion techniques can be categorized in many ways. One convenient means of comparing techniques is to examine the number of 'analog clock cycles' required to produce one effective output sample of the signal being quantized. N° de réf. du vendeur 9780792395133
Quantité disponible : 1 disponible(s)