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Synopsis
In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself.
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Yield Simulation for Integrated Circuits
Edité par
Springer, 1987
ISBN 10 : 0898382440
ISBN 13 : 9780898382440
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Hardcover. Etat : Good. No Jacket. Former library book; Pages can have notes/highlighting. Spine may show signs of wear. ~ ThriftBooks: Read More, Spend Less 1.13. N° de réf. du vendeur G0898382440I3N10
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Yield Simulation for Integrated Circuits
Edité par
Springer, 1987
ISBN 10 : 0898382440
ISBN 13 : 9780898382440
Ancien ou d'occasion
Couverture rigide
Vendeur : Better World Books, Mishawaka, IN, Etats-Unis
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Etat : Good. 1987th Edition. Former library book; may include library markings. Used book that is in clean, average condition without any missing pages. N° de réf. du vendeur 17286753-6
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1987 HC Yield Simulation for Integrated Circuits (The Springer International Series in Engineering and Computer Science, 33)
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Springer, 1987
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ISBN 13 : 9780898382440
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hardcover. Etat : Very Good. Pages are crisp and clean, no marking. Cover is verygood. Binding is tight/good. N° de réf. du vendeur t-pa26
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Yield Simulation for Integrated Circuits (the Springer International Series in Engineering and Computer Science) (Hardcover)
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Springer, 1987
ISBN 10 : 0898382440
ISBN 13 : 9780898382440
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Yield Simulation for Integrated Circuits (The Kluwer International Series in Engineering and Computer Science)
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Kluwer Academic Publishers, Lancaster, United Kingdom, 1987
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ISBN 13 : 9780898382440
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Hardcover. Etat : Good. Etat de la jaquette : No Dust Jacket. First Edition. numerous figures, softening to head of spine, scrape on the bottom of spine, front and back cover, light bump to top corners of cover, FEP is torn off, text and illustrations clean and tight. Ex-Library. N° de réf. du vendeur 098038
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Yield Simulation for Integrated Circuits (The Springer International Series in Engineering and Computer Science, 33)
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Yield Simulation for Integrated Circuits (Hardcover)
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Kluwer Academic Publishers, Dordrecht, 1987
ISBN 10 : 0898382440
ISBN 13 : 9780898382440
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Hardcover. Etat : new. Hardcover. In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. N° de réf. du vendeur 9780898382440
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Yield Simulation for Integrated Circuits (The Springer International Series in Engineering and Computer Science, 33)
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
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Yield Simulation for Integrated Circuits
Edité par
Springer US Sep 1987, 1987
ISBN 10 : 0898382440
ISBN 13 : 9780898382440
Neuf
Couverture rigide
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
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Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. 226 pp. Englisch. N° de réf. du vendeur 9780898382440
Quantité disponible : 2 disponible(s)
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Yield Simulation for Integrated Circuits
Edité par
Kluwer Academic Publishers, 1987
ISBN 10 : 0898382440
ISBN 13 : 9780898382440
Neuf
Couverture rigide
Vendeur : Kennys Bookshop and Art Galleries Ltd., Galway, GY, Irlande
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Etat : New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 209 pages, biography. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 14. Weight in Grams: 498. . 1987. Hardback. . . . . N° de réf. du vendeur V9780898382440
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