Description du livre Gebunden. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides an in-depth treatment of the analysis of interconnect systems, static timing analysis for combinational circuits, timing analysis for sequential circuits, and timing optimization techniques at the transistor and layout levelsProvides an in-d. N� de r�f. du vendeur 4095238

Plus d'informations sur ce vendeur | Contacter le vendeur

Acheter neuf

EUR 162,51

Autre devise

Ajouter au panier

Frais de port : EUR 48,99

De Allemagne vers Etats-Unis

Destinations, frais et d�lais

Image fournie par le vendeur

Timing

Sachin Sapatnekar

Edit� par Springer US Jun 2004 (2004)

ISBN 10 : 1402076711 ISBN 13 : 9781402076718

Neuf Couverture rigide Quantit� disponible : 2

impression � la demande

Vendeur :

BuchWeltWeit Ludwig Meier e.K.
(Bergisch Gladbach, Allemagne)

Evaluation vendeur

Evaluation du vendeur :

Description du livre Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Statistical timing analysis is an area of growing importance in nanometer te- nologies' as the uncertainties associated with process and environmental var- tions increase' and this chapter has captured some of the major efforts in this area. This remains a very active field of research' and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits' a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book' the reader is referred to [LNPS00' HN01' JH01' ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7.1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I + M inputs and O + M outputs. 312 pp. Englisch. N� de r�f. du vendeur 9781402076718

Plus d'informations sur ce vendeur | Contacter le vendeur

Acheter neuf

EUR 192,59

Autre devise

Ajouter au panier

Frais de port : EUR 23

De Allemagne vers Etats-Unis

Destinations, frais et d�lais

Image fournie par le vendeur

Timing

Sachin Sapatnekar

Edit� par Springer US (2004)

ISBN 10 : 1402076711 ISBN 13 : 9781402076718

Neuf Couverture rigide Quantit� disponible : 1

Vendeur :

AHA-BUCH GmbH
(Einbeck, Allemagne)

Evaluation vendeur

Evaluation du vendeur :

Description du livre Buch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Statistical timing analysis is an area of growing importance in nanometer te- nologies' as the uncertainties associated with process and environmental var- tions increase' and this chapter has captured some of the major efforts in this area. This remains a very active field of research' and there is likely to be a great deal of new research to be found in conferences and journals after this book is published. In addition to the statistical analysis of combinational circuits' a good deal of work has been carried out in analyzing the effect of variations on clock skew. Although we will not treat this subject in this book' the reader is referred to [LNPS00' HN01' JH01' ABZ03a] for details. 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in an acyclic network of gates that forms a c- binational logic circuit. A cyclic path in the direction of signal propagation 1 is permitted in the sequential circuit only if it contains at least one register . In general, it is possible to represent any sequential circuit in terms of the schematic shown in Figure 7.1, which has I inputs, O outputs and M registers. The registers outputs feed into the combinational logic which, in turn, feeds the register inputs. Thus, the combinational logic has I + M inputs and O + M outputs. N� de r�f. du vendeur 9781402076718

Plus d'informations sur ce vendeur | Contacter le vendeur

Acheter neuf

EUR 195,81

Autre devise

Ajouter au panier

Frais de port : EUR 32,99

De Allemagne vers Etats-Unis

Destinations, frais et d�lais

Image d'archives