Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated . N� de r�f. du vendeur 4191373

Contacter le vendeur

Acheter neuf

EUR 92,27

Autre devise

Frais de port : EUR 48,99

De Allemagne vers Etats-Unis

Destinations, frais et d�lais

Quantit� disponible : Plus de 20 disponibles

Ajouter au panier

Image fournie par le vendeur

Hierarchical Modeling for VLSI Circuit Testing

John P. Hayes

Edit� par Springer US, 2011

ISBN 10 : 1461288193 ISBN 13 : 9781461288190

Neuf Taschenbuch

Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne

�valuation du vendeur 5 sur 5 �toiles

Taschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models. N� de r�f. du vendeur 9781461288190

Contacter le vendeur

Acheter neuf

EUR 112,77

Autre devise

Frais de port : EUR 29,38

De Allemagne vers Etats-Unis

Destinations, frais et d�lais

Quantit� disponible : 1 disponible(s)

Ajouter au panier

Image d'archives

Hierarchical Modeling for VLSI Circuit Testing

Debashis Bhattacharya

Edit� par Springer-Verlag New York Inc., 2011

ISBN 10 : 1461288193 ISBN 13 : 9781461288190

Neuf Paperback / softback

impression � la demande

Vendeur : THE SAINT BOOKSTORE, Southport, Royaume-Uni

�valuation du vendeur 5 sur 5 �toiles

Paperback / softback. Etat : New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 308. N� de r�f. du vendeur C9781461288190

Contacter le vendeur

Acheter neuf

EUR 138,96

Autre devise

Frais de port : EUR 11,69

De Royaume-Uni vers Etats-Unis

Destinations, frais et d�lais

Quantit� disponible : Plus de 20 disponibles

Ajouter au panier

Image d'archives

Hierarchical Modeling for VLSI Circuit Testing

John P. Hayes Debashis Bhattacharya

Edit� par Springer, 2011

ISBN 10 : 1461288193 ISBN 13 : 9781461288190

Neuf Couverture souple

Vendeur : Books Puddle, New York, NY, Etats-Unis

�valuation du vendeur 4 sur 5 �toiles

Etat : New. pp. 176. N� de r�f. du vendeur 2697768357

Contacter le vendeur

Acheter neuf

EUR 157,23

Autre devise

Frais de port : EUR 3,55

Vers Etats-Unis

Destinations, frais et d�lais

Quantit� disponible : 4 disponible(s)

Ajouter au panier

Image fournie par le vendeur

Hierarchical Modeling for VLSI Circuit Testing

John P. Hayes

Edit� par Springer US Sep 2011, 2011

ISBN 10 : 1461288193 ISBN 13 : 9781461288190

Neuf Taschenbuch

impression � la demande

Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne

�valuation du vendeur 5 sur 5 �toiles

Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models. 176 pp. Englisch. N� de r�f. du vendeur 9781461288190

Contacter le vendeur

Acheter neuf

EUR 139,05

Autre devise

Frais de port : EUR 23

De Allemagne vers Etats-Unis

Destinations, frais et d�lais

Quantit� disponible : 2 disponible(s)

Ajouter au panier

Image d'archives

Hierarchical Modeling for VLSI Circuit Testing

Hayes John P. Bhattacharya Debashis

Edit� par Springer, 2011

ISBN 10 : 1461288193 ISBN 13 : 9781461288190

Neuf Couverture souple

impression � la demande

Vendeur : Majestic Books, Hounslow, Royaume-Uni

�valuation du vendeur 5 sur 5 �toiles

Etat : New. Print on Demand pp. 176 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam. N� de r�f. du vendeur 94661754

Contacter le vendeur