Taschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley. N� de r�f. du vendeur 9781461376064

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Formal Equivalence Checking & Design Debugging (Frontiers in Electronic Testin) (Frontiers in Electronic Testing) by Huang, Shi-Yu [Paperback ]

Huang, Shi-Yu

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ISBN 10 : 1461376068 ISBN 13 : 9781461376064

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Formal Equivalence Checking and Design Debugging

Kwang-Ting (Tim) Cheng

Edit� par Springer US Sep 2012, 2012

ISBN 10 : 1461376068 ISBN 13 : 9781461376064

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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley 252 pp. Englisch. N� de r�f. du vendeur 9781461376064

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Formal Equivalence Checking and Design Debugging

Huang, Shi-Yu; Cheng, Kwang-Ting

Edit� par Springer, 2012

ISBN 10 : 1461376068 ISBN 13 : 9781461376064

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Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing, 12)

Shi-Yu Huang; Kwang-Ting (Tim) Cheng

Edit� par Springer, 2012

ISBN 10 : 1461376068 ISBN 13 : 9781461376064

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Formal Equivalence Checking and Design Debugging

Shi-Yu Huang|Kwang-Ting (Tim) Cheng

Edit� par Springer US, 2012

ISBN 10 : 1461376068 ISBN 13 : 9781461376064

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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and . N� de r�f. du vendeur 4195734

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