SYSTEMC IMPLEMENTATION OF A RISC-BASED PROCESSOR ARCHITECTURE: DESIGN AND IMPLEMENTATION OF A 16-BIT RISC-BASED PROCESSOR ARCHITECTURE WITH SYSTEMC LANGUAGE - Couverture souple

Zengin, Salih

 
9783639130355: SYSTEMC IMPLEMENTATION OF A RISC-BASED PROCESSOR ARCHITECTURE: DESIGN AND IMPLEMENTATION OF A 16-BIT RISC-BASED PROCESSOR ARCHITECTURE WITH SYSTEMC LANGUAGE
Couverture souple
ISBN 10 : 3639130359 ISBN 13 : 9783639130355
Editeur : VDM Verlag, 2009

Synopsis

Increasing the complexity of the electronic systems leads to electronic system level modeling concept supporting hardware and software co-design and co-verification environment in a single framework. SystemC, an IEEE approved electronic design standard for system design and verification processes, provides such an environment by supporting a wide range of abstraction levels from system-level to register-transfer level. In this book, two different models of a processor core, whose instruction set architecture is compatible with TI MSP430 microcontroller, are designed by employing the classical hardware modeling capability of the SystemC. With its well-designed orthogonal instruction set, elegant addressing modes, useful constant generators and flexible von-Neumann architecture, 16-bit RISC-like processor of the MSP430 microcontroller is an ideal selection for the SoC designs. Instruction set and addressing modes of the designed processors are simulated thoroughly. Moreover, original CRC programs are used to verify the processor cores. SystemC to hardware flow is also illustrated by synthesizing the ALU part of the processor into a Xilinx-based hardware.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Increasing the complexity of the electronic systems leads to electronic system level modeling concept supporting hardware and software co-design and co-verification environment in a single framework. SystemC, an IEEE approved electronic design standard for system design and verification processes, provides such an environment by supporting a wide range of abstraction levels from system-level to register-transfer level. In this book, two different models of a processor core, whose instruction set architecture is compatible with TI MSP430 microcontroller, are designed by employing the classical hardware modeling capability of the SystemC. With its well-designed orthogonal instruction set, elegant addressing modes, useful constant generators and flexible von-Neumann architecture, 16-bit RISC-like processor of the MSP430 microcontroller is an ideal selection for the SoC designs. Instruction set and addressing modes of the designed processors are simulated thoroughly. Moreover, original CRC programs are used to verify the processor cores. SystemC to hardware flow is also illustrated by synthesizing the ALU part of the processor into a Xilinx-based hardware.

Biographie de l'auteur

He was born in 1979 and he received B.S. and M.S. degrees in Electrical and Electronics Engineering at Middle East Technical University(METU),Turkey in 2003 and 2006 respectively. He is currently pursuing his Ph.D. at METU and his main interest areas are SystemC,computer architectures,multi- processor systems and their network applications.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
VDM Verlag
Date d'édition
2009
Langue
anglais
ISBN 10 
3639130359
ISBN 13 
9783639130355
Reliure
Broché
Nombre de pages
200
Coordonnées du fabricant
non disponible
Personne responsable
non disponible