EUR 13,07 expédition depuis Chine vers France
Destinations, frais et délaisVendeur : liu xing, Nanjing, JS, Chine
paperback. Etat : New. Paperback. Pub Date: 2005 Pages: 710 Language: Chinese in Publisher: Electronic Industry Press book explained by a large number of complete instances the use VerilogHDL VLSI design structured modeling method. key steps and design verification method and other useful content. The book is divided into 11 chapters. covering modeling. structural balance. functional verification. fault simulation. and logic synthesis. and other key issues. as well as after the comprehensive design validation. timi. N° de réf. du vendeur CB022334
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Vendeur : dsmbooks, Liverpool, Royaume-Uni
paperback. Etat : New. New. book. N° de réf. du vendeur D8S0-3-M-7505399179-6
Quantité disponible : 1 disponible(s)