The Core Test Wrapper Handbook

Francisco Da Silva

ISBN 10: 148998769X / ISBN 13: 9781489987693

Edité par Springer US Okt 2014, 2014

A propos de cet article

This item is printed on demand - it takes 3-4 days longer - Neuware -The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500tm provides insight into the rules and recommendations of IEEE Std. 1500. This book focuses on practical design considerations inherent to the application of IEEE Std. 1500 by discussing design choices and other decisions relevant to this IEEE standard. The authors provide background information about some of the choices and decisions made throughout the design of IEEE Std. 1500. 308 pp. Englisch.

N° de réf. du vendeur 9781489987693

Détails bibliographiques

• Titre: The Core Test Wrapper Handbook
• Éditeur: Springer US Okt 2014
• Date de parution: 2014
• Langue: anglais
• ISBN à 10 chiffres: 148998769X
• ISBN à 13 chiffres: 9781489987693
• Reliure: Taschenbuch
• État de l'article: Neu
• Dimensions: 235 L x 155 H x 17 P (en millimètres) 235 millimètres de largeur par 155 millimètres de hauteur par 17 millimètres de profondeur
• Poids: 470 grammes

A propos de ce titre

Synopsis

In the early to mid-1990's while working at what was then Motorola Se- conductor, business changes forced my multi-hundred dollar microprocessor to become a tens-of-dollars embedded core. I ran into first hand the problem of trying to deliver what used to be a whole chip with something on the order of over 400 interconnect signals to a design team that was going to stuff it into a package with less than 220 signal pins and surround it with other logic. I also ran into the problem of delivering microprocessor specification verifi- tion – a microprocessor is not just about the functions and instructions included with the instruction set, but also the MIPs rating at some given f- quency. I faced two dilemmas: one, I could not deliver functional vectors without significant development of off-core logic to deal with the reduced chip I/O map (and everybody's I/O map was going to be a little different); and two, the JTAG (1149. 1) boundary scan ring that was around my core when it was a chip was going to be woefully inadequate since it did not support - speed signal application and capture and independent use separate from my core. I considered the problem at length and came up with my own solution that was predominantly a separate non-JTAG scan test wrapper that supported at-speed application of launch-capture cycles using the system clock. But my problems weren't over at that point either.