Defect-oriented Testing for Nano-metric CMOS VLSI Circuits
Sachdev, Manoj; Gyvez, Jose Pineda de
ISBN 10: 1441942858 ISBN 13: 9781441942852
Edité par Springer-Verlag New York Inc., 2010
Neuf(s)
Couverture souple
Vendeur
Kennys Bookshop and Art Galleries Ltd., Galway, GY, Irlande
Évaluation du vendeur 5 sur 5 étoiles
Vendeur AbeBooks depuis 27 février 2001
Cet article spécifique n'est plus disponible.
A propos de cet article
Description :
Series: Frontiers in Electronic Testing. Num Pages: 349 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational. Dimension: 234 x 156 x 18. Weight in Grams: 539. . 2010. Softcover reprint of hardcover 2nd ed. 2007. paperback. . . . . N° de réf. du vendeur V9781441942852
Synopsis :
This book is essential to understand new test methodologies, algorithms and industrial practices. Without its insight into the physics of nano-metric technologies, it would be difficult to develop system-level test strategies that yield a high IC fault coverage. The work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. The 2nd edition of Defect Oriented Testing has been extensively updated with the addition of chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering to provide a link between defect sources and yield. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.
Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.
Détails bibliographiques
Titre : Defect-oriented Testing for Nano-metric CMOS...
Éditeur : Springer-Verlag New York Inc.
Date d'édition : 2010
Reliure : Couverture souple
Etat : New
Meilleurs résultats de recherche sur AbeBooks
Image d'archives
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing, 34)
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. In. N° de réf. du vendeur ria9781441942852_new
Acheter neuf
EUR 156,82
Frais de port :
EUR 13,60
De Royaume-Uni vers Etats-Unis
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
impression à la demandeVendeur : moluna, Greven, Allemagne
Évaluation du vendeur 4 sur 5 étoiles
Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Wide coverage of topics in test engineeringUnique defect-oriented focus of the materialsIntroduction to yield engineering common practicesThe 2nd edition of defect oriented testing has been extensively updated. New cha. N° de réf. du vendeur 4174637
Acheter neuf
EUR 180,07
Frais de port :
EUR 48,99
De Allemagne vers Etats-Unis
Quantité disponible : Plus de 20 disponibles
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Vendeur : preigu, Osnabrück, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits | José Pineda de Gyvez (u. a.) | Taschenbuch | xxi | Englisch | 2010 | Springer US | EAN 9781441942852 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu. N° de réf. du vendeur 107220672
Acheter neuf
EUR 186,80
Frais de port :
EUR 70
De Allemagne vers Etats-Unis
Quantité disponible : 5 disponible(s)
Image d'archives
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing, 34)
Vendeur : Best Price, Torrance, CA, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. SUPER FAST SHIPPING. N° de réf. du vendeur 9781441942852
Acheter neuf
EUR 194,09
Frais de port :
EUR 7,75
Vers Etats-Unis
Quantité disponible : 2 disponible(s)
Image d'archives
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing, 34)
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur ABLIING23Mar2411530295755
Acheter neuf
EUR 204,66
Frais de port :
EUR 3,44
Vers Etats-Unis
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Edité par
Springer US, Springer New York Nov 2010, 2010
ISBN 10 : 1441942858
ISBN 13 : 9781441942852
Neuf
Taschenbuch
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent. 352 pp. Englisch. N° de réf. du vendeur 9781441942852
Acheter neuf
EUR 213,99
Frais de port :
EUR 23
De Allemagne vers Etats-Unis
Quantité disponible : 2 disponible(s)
Image fournie par le vendeur
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Edité par
Springer US, Springer New York Nov 2010, 2010
ISBN 10 : 1441942858
ISBN 13 : 9781441942852
Neuf
Taschenbuch
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 352 pp. Englisch. N° de réf. du vendeur 9781441942852
Acheter neuf
EUR 213,99
Frais de port :
EUR 60
De Allemagne vers Etats-Unis
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent. N° de réf. du vendeur 9781441942852
Acheter neuf
EUR 223,11
Frais de port :
EUR 62,67
De Allemagne vers Etats-Unis
Quantité disponible : 1 disponible(s)
Image d'archives
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Vendeur : Revaluation Books, Exeter, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Paperback. Etat : Brand New. 2nd edition. 349 pages. 9.10x6.10x0.90 inches. In Stock. N° de réf. du vendeur x-1441942858
Acheter neuf
EUR 301,62
Frais de port :
EUR 14,19
De Royaume-Uni vers Etats-Unis
Quantité disponible : 2 disponible(s)
Image d'archives
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing (34))
Edité par
Springer, 2010
ISBN 10 : 1441942858
ISBN 13 : 9781441942852
Ancien ou d'occasion
Paperback
Vendeur : Mispah books, Redhill, SURRE, Royaume-Uni
Évaluation du vendeur 4 sur 5 étoiles
Paperback. Etat : Like New. Like New. book. N° de réf. du vendeur ERICA78714419428586
Acheter D'occasion
EUR 303,99
Frais de port :
EUR 28,38
De Royaume-Uni vers Etats-Unis
Quantité disponible : 1 disponible(s)