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Description du livre Etat : New. N° de réf. du vendeur 20196167-n
Description du livre Soft Cover. Etat : new. N° de réf. du vendeur 9781461288985
Description du livre Etat : New. N° de réf. du vendeur ABLIING23Mar2716030030114
Description du livre Etat : New. PRINT ON DEMAND Book; New; Fast Shipping from the UK. No. book. N° de réf. du vendeur ria9781461288985_lsuk
Description du livre Taschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - From the perspective of complex systems, conventional Ie's can be regarded as 'discrete' devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term 'wafer level' is perhaps more appropriate than 'wafer-scale'. A 'wafer-level' monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, 'wafer-scale' merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit. N° de réf. du vendeur 9781461288985
Description du livre Etat : New. N° de réf. du vendeur 20196167-n
Description du livre Paperback / softback. Etat : New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days. N° de réf. du vendeur C9781461288985
Description du livre Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -From the perspective of complex systems, conventional Ie's can be regarded as 'discrete' devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term 'wafer level' is perhaps more appropriate than 'wafer-scale'. A 'wafer-level' monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, 'wafer-scale' merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit. 476 pp. Englisch. N° de réf. du vendeur 9781461288985
Description du livre Etat : New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 456 pages, biography. BIC Classification: THR; TJFC. Category: (G) General (US: Trade). Dimension: 235 x 155 x 24. Weight in Grams: 724. . 2012. Softcover reprint of the original 1st ed. 1989. Paperback. . . . . N° de réf. du vendeur V9781461288985
Description du livre Etat : New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 456 pages, biography. BIC Classification: THR; TJFC. Category: (G) General (US: Trade). Dimension: 235 x 155 x 24. Weight in Grams: 724. . 2012. Softcover reprint of the original 1st ed. 1989. Paperback. . . . . Books ship from the US and Ireland. N° de réf. du vendeur V9781461288985