Articles liés à Power Integrity for Nanoscale Integrated Systems

Power Integrity for Nanoscale Integrated Systems - Couverture rigide

HASHIMOTO

 
9780071787765: Power Integrity for Nanoscale Integrated Systems

Synopsis

Publisher's Note: Products purchased from Third Party sellers are not guaranteed by the publisher for quality, authenticity, or access to any online entitlements included with the product.Proven methods for noise-tolerant nanoscale integrated circuit design

This leading-edge guide discusses the impact of power integrity from a design perspective, emphasizing phenomena and problems induced by power integrity degradation and the latest design trends, including low-power design. Power Integrity for Nanoscale Integrated Systems describes how these problems can be forecast early in the design process and the countermeasures that can be used to address them, such as the inclusion of inductance and accurate modeling for PI analysis, as well as robust circuit design. Detailed examples and a case study on the IBM POWER7+ processor illustrate real-world applications of the techniques presented in this practical resource.

Coverage includes:

  • Significance of power integrity for integrated circuits
  • Supply and substrate noise impact on circuits
  • Clock generation and distribution with power integrity
  • Signal and power integrity design for I/O circuits
  • Power integrity degradation and modeling
  • Lumped, distributed, and 3D modeling for power integrity
  • Chip temperature and PI impact
  • Low-power techniques and PI impact
  • Power integrity case study using the IBM POWER7+ processor chip
  • Carbon nanotube interconnects for power delivery

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

À propos de l'auteur

Masanori Hashimoto is an Associate Professor in the department of Information Systems and Engineering, Graduate School of Information Science Technology, Osaka University. He has been working on modeling and measurement of on-chip power supply noise and signal coupling noise. Professor Hashimoto's research interests include timing, power, and signal integrity analysis, ultra-low power design, design for reliability, performance optimization in physical design, and on-chip high-speed signaling. He has co-authored several journal articles.

Raj Nair, a consultant in IC power delivery and power integrity, is co-founder of Anasim Corporation, which commercializes power integrity and energy aware SoC (System on Chip) design tools.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.