Fundamentals of Digital Logic With Verilog Design - Couverture rigide

Brown, Stephen; Vranesic, Zvonko

Couverture rigide

ISBN 10 : 0077211642 ISBN 13 : 9780077211646

Editeur : McGraw-Hill Professional, 2007

Synopsis

Fundamentals of Digital Logic With Verilog Design teaches the basic design techniques for logic circuits. It emphasizes the synthesis of circuits and explains how circuits are implemented in real chips. Fundamental concepts are illustrated by using small examples.

Use of CAD software is well integrated into the book. A CD-ROM that contains Altera's Quartus CAD software comes free with every copy of the text. The CAD software provides automatic mapping of a design written in Verilog into Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). Students will be able to try, firsthand, the book's Verilog examples (over 140) and homework problems.

Engineers use Quartus CAD for designing, simulating, testing and implementing logic circuits. The version included with this text supports all major features of the commercial product and comes with a compiler for the IEEE standard Verilog language. Students will be able to:

enter a design into the CAD system

compile the design into a selected device

simulate the functionality and timing of the resulting circuit

implement the designs in actual devices (using the school's laboratory facilities)

Verilog is a complex language, so it is introduced gradually in the book. Each Verilog feature is presented as it becomes pertinent for the circuits being discussed. To teach the student to use the Quartus CAD, the book includes three tutorials.

A propos du livre

À propos de l?auteur

Zvonko Vranesic (Toronto, Canada) Professor of Computer Engineering at Toronto University, Canada.

Détails de l'édition

• Éditeur: McGraw-Hill Professional
• Date d'édition: 2007
• Langue: anglais
• ISBN 10: 0077211642
• ISBN 13: 9780077211646
• Reliure: Relié
• Numéro d'édition: 2
• Nombre de pages: 960
• Coordonnées du fabricant: non disponible
• Personne responsable: non disponible