System-On-Chip Test Architectures: Nanometer Design for Testability - Couverture rigide

Wang, Laung-Terng; Stroud, Charles E.; Touba, Nur A.

 
9780123739735: System-On-Chip Test Architectures: Nanometer Design for Testability
Couverture rigide
ISBN 10 : 012373973X ISBN 13 : 9780123739735
Editeur : Morgan Kaufmann Publishers In, 2008

Synopsis

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

À propos de l?auteur

Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
Morgan Kaufmann Publishers In
Date d'édition
2008
Langue
anglais
ISBN 10 
012373973X
ISBN 13 
9780123739735
Reliure
Relié
Numéro d'édition
1
Nombre de pages
896
Coordonnées du fabricant
non disponible
Personne responsable
non disponible