Synopsis
This book will explain how to verify SoC (Systems on Chip) logic designs using 'formal' and 'semiformal' verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in 'functional' verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
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Présentation de l'éditeur
This book will explain how to verify SoC (Systems on Chip) logic designs using 'formal' and 'semiformal' verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in 'functional' verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
Biographie de l'auteur
*Spent 15 years at Fujitsu research laboratories.*Research on synthesis and verification of digital systems for more than 25 years*Full professor at VLSI Design and Education Center in the University of Tokyo
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Verification Techniques for System-Level Design
Vendeur : Revaluation Books, Exeter, Royaume-Uni
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Paperback. Etat : Brand New. 250 pages. 9.25x7.50x0.57 inches. In Stock. N° de réf. du vendeur zk0124054617
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