Verilog Hdl: A Guide to Digital Design and Synthesis - Couverture rigide

Palnitkar, Samir

Couverture rigide

ISBN 10 : 0130449113 ISBN 13 : 9780130449115

Editeur : Prentice Hall, 2003

Synopsis

Verilog HDL is a language for digital design, just as C is a language for programming. This complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design. Palnitkar covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis. Verilog HDL is a hardware description language (with a user community of more than 50,000 active designers) used to design and document electronic systems. This completely updated reference progresses from basic to advanced concepts in digital design, including timing simulation, switch level modeling, PLI, and logic synthesis.

A propos du livre

À propos de l?auteur

About the Author

Samir Palnitkar is a recognized authority on Verilog HDL, modeling, verification, logic synthesis, and EDA-based methodologies in digital design. He has worked extensively with design and verification on various successful microprocessor, ASIC, and system projects. He was the lead developer of the Verilog framework for the shared memory, cache coherent, multiprocessor architecture, popularly known as the UltraSPARCTM Port Architecture, defined for Sun's next generation UltraSPARC-based desktop systems. Besides the UltraSPARC CPU, he has worked on a number of diverse design and verification projects at leading companies including Cisco, Philips, Mitsubishi, Motorola, National, Advanced Micro Devices, and Standard Microsystems.

Détails de l'édition

• Éditeur: Prentice Hall
• Date d'édition: 2003
• ISBN 10: 0130449113
• ISBN 13: 9780130449115
• Reliure: Relié
• Langue: anglais
• Numéro d'édition: 2
• Nombre de pages: 496
• Coordonnées du fabricant: non disponible