This volume provides the reader with a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, techniques for estimating and relieving congestion, and a critical analysis of the accuracy and effectiveness of these techniques. Readers are supplied with the knowledge to prudently choose an approach that is appropriate to their design goals. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing phase. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques.
Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.
Gratuit expédition depuis Allemagne vers France
Destinations, frais et délaisGratuit expédition depuis Etats-Unis vers France
Destinations, frais et délaisVendeur : Romtrade Corp., STERLING HEIGHTS, MI, Etats-Unis
Etat : New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide. N° de réf. du vendeur ABNR-76723
Quantité disponible : 5 disponible(s)
Vendeur : Basi6 International, Irving, TX, Etats-Unis
Etat : Brand New. New. US edition. Expediting shipping for all USA and Europe orders excluding PO Box. Excellent Customer Service. N° de réf. du vendeur ABEJUNE24-85477
Quantité disponible : Plus de 20 disponibles
Vendeur : Buchpark, Trebbin, Allemagne
Etat : Sehr gut. Zustand: Sehr gut - Neubindung, Buchrücken leicht angestossen | Seiten: 250 | Sprache: Englisch | Produktart: Bücher. N° de réf. du vendeur 2975617/12
Quantité disponible : 1 disponible(s)
Vendeur : Romtrade Corp., STERLING HEIGHTS, MI, Etats-Unis
Etat : New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide. N° de réf. du vendeur ABNR-91058
Quantité disponible : 1 disponible(s)
Vendeur : Basi6 International, Irving, TX, Etats-Unis
Etat : Brand New. New. US edition. Expediting shipping for all USA and Europe orders excluding PO Box. Excellent Customer Service. N° de réf. du vendeur ABEJUNE24-85478
Quantité disponible : 1 disponible(s)
Vendeur : BennettBooksLtd, North Las Vegas, NV, Etats-Unis
hardcover. Etat : New. In shrink wrap. Looks like an interesting title! N° de réf. du vendeur Q-0387300376
Quantité disponible : 1 disponible(s)
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Etat : New. In. N° de réf. du vendeur ria9780387300375_new
Quantité disponible : Plus de 20 disponibles
Vendeur : moluna, Greven, Allemagne
Gebunden. Etat : New. Provides an in-depth treatment of routing congestion in VLSI circuitsComprehensively surveys the work done and points to challenges for the futureEquips readers with the knowledge to prudently choose an approach that is appropriate to their. N° de réf. du vendeur 5909831
Quantité disponible : Plus de 20 disponibles
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
Etat : New. N° de réf. du vendeur ABLIING23Feb2215580171689
Quantité disponible : Plus de 20 disponibles
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Buch. Etat : Neu. Neuware - With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid 'tra c jams'; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ow congestion-aware. The book explores this tradeo that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a circuit, while still ensuring that the circuit remains routable It begins by motivating the c- gestion problem, explaining why this problem is important and how it will trend. It then progresses with comprehensive discussions of the techniques available for estimating and optimizing congestion at various stages in the design ow. N° de réf. du vendeur 9780387300375
Quantité disponible : 2 disponible(s)