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Synopsis
iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques.
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- ÉditeurSpringer-Verlag New York Inc.
- Date d'édition2009
- ISBN 10 0387938192
- ISBN 13 9780387938196
- ReliureRelié
- Langueanglais
- Nombre de pages572
- Coordonnées du fabricantnon disponible
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Static Timing Analysis for Nanometer Designs: A Practical Approach
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Static Timing Analysis for Nanometer Designs
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Gebunden. Etat : New. Provides a reference for engineers in the field of static timing analysis for semiconductorsDiscusses the underlying theoretical background as well as in-depth coverage of timing verification using static timing analysisCovers topics such a. N° de réf. du vendeur 5911854
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Static Timing Analysis for Nanometer Designs: A Practical Approach
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ISBN 10 : 0387938192
ISBN 13 : 9780387938196
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Static Timing Analysis for Nanometer Designs : A Practical Approach
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ISBN 10 : 0387938192
ISBN 13 : 9780387938196
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Buch. Etat : Neu. Neuware - iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques. N° de réf. du vendeur 9780387938196
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