Recent advances in very large scale integrated (VLSI) circuit technology have resulted in complex chips with millions of interconnections packed onto a single chip. This causes many problems, including unwanted capacitances, inductances, cross-talk and propagation delays, all of which have serious effects on processor performance. This text is devoted solely to the modelling, analysis and computer simulation of high-speed VLSI interconnections. Source codes of several computer programs for simulating VLSI interconnections and challenging exercises are included at the end of each chapter.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
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