Articles liés à Digital Timing Macromodeling for Vlsi Design Verification
- ÉditeurSpringer
- Date d'édition1995
- ISBN 10 0792395808
- ISBN 13 9780792395805
- ReliureRelié
- Langueanglais
- Nombre de pages265
Acheter neuf
Afficher cet article
EUR 162,38
EUR 3,52 expédition vers Etats-Unis
Destinations, frais et délais
Résultats de recherche pour Digital Timing Macromodeling for Vlsi Design Verification
Image d'archives
Digital Timing Macromodeling for VLSI Design Verification (Kluwer International Series in Engineering and Computer Science. VLSI, Computer Architecture and Digital Signal Processing)
Edité par
Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A., 1995
ISBN 10 : 0792395808
ISBN 13 : 9780792395805
Ancien ou d'occasion
Couverture rigide
Edition originale
Vendeur : PsychoBabel & Skoob Books, Didcot, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
hardcover. Etat : Very Good. Etat de la jaquette : No Dust Jacket. First Edition. White hardcover with white lettering on spine and upper board and contents in very good clean condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T. Used. N° de réf. du vendeur 249216
Quantité disponible : 1 disponible(s)
Image d'archives
Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science, 319)
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur ABLIING23Feb2416190186024
Quantité disponible : Plus de 20 disponibles
Image d'archives
Digital Timing Macromodeling for VLSI Design Verification
Edité par
Springer US, 1995
ISBN 10 : 0792395808
ISBN 13 : 9780792395805
Ancien ou d'occasion
Couverture rigide
Vendeur : Buchpark, Trebbin, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Etat : Gut. Zustand: Gut - Gebrauchs- und Lagerspuren. Außen: verschmutzt, angestoßen. Innen: Seiten verschmutzt, Geknickt. | Seiten: 292 | Sprache: Englisch | Produktart: Bücher. N° de réf. du vendeur 2297973/3
Quantité disponible : 2 disponible(s)
Image d'archives
Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science, 319)
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. In. N° de réf. du vendeur ria9780792395805_new
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Digital Timing Macromodeling for VLSI Design Verification
impression à la demandeVendeur : moluna, Greven, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Gebunden. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timi. N° de réf. du vendeur 5971598
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Digital Timing Macromodeling for VLSI Design Verification
Edité par
Springer US, Springer US, 1995
ISBN 10 : 0792395808
ISBN 13 : 9780792395805
Neuf
Couverture rigide
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Buch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. N° de réf. du vendeur 9780792395805
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
Digital Timing Macromodeling for VLSI Design Verification
Edité par
Springer US Mai 1995, 1995
ISBN 10 : 0792395808
ISBN 13 : 9780792395805
Neuf
Couverture rigide
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. 292 pp. Englisch. N° de réf. du vendeur 9780792395805
Quantité disponible : 2 disponible(s)
Image d'archives
Digital Timing Macromodeling for VLSI Design Verification
Vendeur : Books Puddle, New York, NY, Etats-Unis
Évaluation du vendeur 4 sur 5 étoiles
Etat : New. pp. 292 Index. N° de réf. du vendeur 26319980
Quantité disponible : 4 disponible(s)
Image d'archives
Digital Timing Macromodeling for VLSI Design Verification
impression à la demandeVendeur : Majestic Books, Hounslow, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. Print on Demand pp. 292 Figures, 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam. N° de réf. du vendeur 7560755
Quantité disponible : 4 disponible(s)
Image d'archives
Digital Timing Macromodeling for VLSI Design Verification
impression à la demandeVendeur : Biblios, Frankfurt am main, HESSE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. PRINT ON DEMAND pp. 292. N° de réf. du vendeur 18319974
Quantité disponible : 4 disponible(s)