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Synopsis
In the early days of VLSI, the design of the power distribution for an integrated cir- cuit was rather simple. Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi- vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler. Few available wiring layers forced floorplans that allowed simple, planar (non-over- lapping) power networks. Lower speeds and circuit density made the choice of the wire widths easier: we made them just fat enough to avoid resistive voltage drops due to switching currents in the supply network. And we just didn't need enormous num- bers of power and ground pins on the package for the chips to work. It's not so simple any more. Increased integration has forced us to focus on reliability concerns such as metal elec- tromigration, which affects wire sizing decisions in the power network. Extra metal layers have allowed more flexibility in the topological layout of the power networks.
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Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICS
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Springer, 1996
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ISBN 13 : 9780792397342
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Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
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Springer, 1996
ISBN 10 : 0792397347
ISBN 13 : 9780792397342
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Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal Ics
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Springer, 1996
ISBN 10 : 0792397347
ISBN 13 : 9780792397342
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Etat : Très bon. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal Ics| Stanisic, Balsha R.; Rutenbar, Rob A.; Carley, L. Richard | Kluwer, 1996. In-8° cartonné, 206p . Couverture propre . Dos solide. Intérieur frais sans soulignage ou annotation. Exemplaire de bibliothèque : petit code barre en pied de 1re de couv., cotation au dos, rares et discrets petits tampons à l'intérieur de l'ouvrage.Très bon état général pour cet ouvrage. [Ba 52]. N° de réf. du vendeur FV-5WCJ-7UD4
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Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
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Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
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Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
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Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
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Buch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -In the early days of VLSI, the design of the power distribution for an integrated cir cuit was rather simple. Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler. Few available wiring layers forced floorplans that allowed simple, planar (non-over lapping) power networks. Lower speeds and circuit density made the choice of the wire widths easier: we made them just fat enough to avoid resistive voltage drops due to switching currents in the supply network. And we just didn't need enormous num bers of power and ground pins on the package for the chips to work. It's not so simple any more. Increased integration has forced us to focus on reliability concerns such as metal elec tromigration, which affects wire sizing decisions in the power network. Extra metal layers have allowed more flexibility in the topological layout of the power networks.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 236 pp. Englisch. N° de réf. du vendeur 9780792397342
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Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
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ISBN 10 : 0792397347
ISBN 13 : 9780792397342
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Buch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - In the early days of VLSI, the design of the power distribution for an integrated cir cuit was rather simple. Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler. Few available wiring layers forced floorplans that allowed simple, planar (non-over lapping) power networks. Lower speeds and circuit density made the choice of the wire widths easier: we made them just fat enough to avoid resistive voltage drops due to switching currents in the supply network. And we just didn't need enormous num bers of power and ground pins on the package for the chips to work. It's not so simple any more. Increased integration has forced us to focus on reliability concerns such as metal elec tromigration, which affects wire sizing decisions in the power network. Extra metal layers have allowed more flexibility in the topological layout of the power networks. N° de réf. du vendeur 9780792397342
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