Articles liés à Vlsi Fault Modeling and Testing Techniques
Synopsis
VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.
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brist /f George /i W.
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VLSI Fault Modeling and Testing Techniques: (VLSI Design Automation Series)
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Praeger, 1993
ISBN 10 : 0893917818
ISBN 13 : 9780893917814
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VLSI Fault Modeling and Testing Techniques
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ISBN 13 : 9780893917814
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Gebunden. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. This text explores VLSI fault modelling and testing techniques and covers such topics as: physical fault modelling and simulation for VSLI MOS circuits designing CMOS gates to test open faults testing bridging faults in VLSI and testable design synthesis. N° de réf. du vendeur 447101356
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Vlsi Fault Modeling and Testing Techniques
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VLSI Fault Modeling and Testing Techniques: (VLSI Design Automation Series)
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Vlsi Fault Modeling and Testing Techniques
Edité par
Praeger, 1993
ISBN 10 : 0893917818
ISBN 13 : 9780893917814
Ancien ou d'occasion
Couverture rigide
Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
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VLSI Fault Modeling and Testing Techniques
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Buch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed. N° de réf. du vendeur 9780893917814
Quantité disponible : 1 disponible(s)
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Vlsi Fault Modeling and Testing Techniques
Edité par
Praeger, 1993
ISBN 10 : 0893917818
ISBN 13 : 9780893917814
Ancien ou d'occasion
Couverture rigide
Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
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Etat : As New. Unread book in perfect condition. N° de réf. du vendeur 823827
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Vlsi Fault Modeling and Testing Techniques
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Vlsi Fault Modeling and Testing Techniques
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VLSI Fault Modeling and Testing Techniques (Hardcover)
Edité par
Bloomsbury Publishing Plc, Westport, 1993
ISBN 10 : 0893917818
ISBN 13 : 9780893917814
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Hardcover. Etat : new. Hardcover. VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed. This text explores VLSI fault modelling and testing techniques and covers such topics as: physical fault modelling and simulation for VSLI MOS circuits; designing CMOS gates to test open faults; testing bridging faults in VLSI; and testable design synthesis models. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability. N° de réf. du vendeur 9780893917814
Quantité disponible : 1 disponible(s)