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Synopsis
This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu- tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors.
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A Systolic Array Optimizing Compiler
Edité par
Kluwer Academic Publishers, 1989
ISBN 10 : 0898383005
ISBN 13 : 9780898383003
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Hardcover. Etat : Très bon. Ancien livre de bibliothèque. Petite(s) trace(s) de pliure sur la couverture. Légères traces d'usure sur la couverture. Edition 1989. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Very good. Former library book. Slightly creased cover. Slight signs of wear on the cover. Edition 1989. Ammareal gives back up to 15% of this item's net price to charity organizations. N° de réf. du vendeur E-812-853
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A Systolic Array Optimizing Compiler (The Springer International Series in Engineering and Computer Science)
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Springer, 1989
ISBN 10 : 0898383005
ISBN 13 : 9780898383003
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Hardcover. Etat : Very Good. Dust Jacket may NOT BE INCLUDED.CDs may be missing. book. N° de réf. du vendeur ERICA82708983830053
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A Systolic Array Optimizing Compiler
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Springer US Jan 1989, 1989
ISBN 10 : 0898383005
ISBN 13 : 9780898383003
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Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
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Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors. 228 pp. Englisch. N° de réf. du vendeur 9780898383003
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A Systolic Array Optimizing Compiler (The Springer International Series in Engineering and Computer Science, 64)
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
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A Systolic Array Optimizing Compiler
Edité par
Springer US, Springer US Jan 1989, 1989
ISBN 10 : 0898383005
ISBN 13 : 9780898383003
Neuf
Couverture rigide
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Buch. Etat : Neu. Neuware -This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 228 pp. Englisch. N° de réf. du vendeur 9780898383003
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A Systolic Array Optimizing Compiler
Edité par
Springer US, Springer US, 1989
ISBN 10 : 0898383005
ISBN 13 : 9780898383003
Neuf
Couverture rigide
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
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Buch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors. N° de réf. du vendeur 9780898383003
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A Systolic Array Optimizing Compiler
Edité par
Kluwer Academic Publishers, 1989
ISBN 10 : 0898383005
ISBN 13 : 9780898383003
Neuf
Couverture rigide
Vendeur : THE SAINT BOOKSTORE, Southport, Royaume-Uni
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Hardback. Etat : New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 528. N° de réf. du vendeur C9780898383003
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A Systolic Array Optimizing Compiler
impression à la demandeVendeur : Majestic Books, Hounslow, Royaume-Uni
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Etat : New. Print on Demand pp. 228 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam. N° de réf. du vendeur 5845930
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A Systolic Array Optimizing Compiler
impression à la demandeVendeur : Biblios, Frankfurt am main, HESSE, Allemagne
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Etat : New. PRINT ON DEMAND pp. 228. N° de réf. du vendeur 183050623
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A Systolic Array Optimizing Compiler (The Springer International Series in Engineering and Computer Science, 64)
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
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