No A Systolic Array Optimizing Compiler Read a customer review or write one .
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EUR 10 expédition depuis France vers Etats-Unis
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Destinations, frais et délaisVendeur : Ammareal, Morangis, France
Hardcover. Etat : Très bon. Ancien livre de bibliothèque. Petite(s) trace(s) de pliure sur la couverture. Légères traces d'usure sur la couverture. Edition 1989. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Very good. Former library book. Slightly creased cover. Slight signs of wear on the cover. Edition 1989. Ammareal gives back up to 15% of this item's net price to charity organizations. N° de réf. du vendeur E-812-853
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Vendeur : thebookforest.com, San Rafael, CA, Etats-Unis
Etat : New. Well packaged and promptly shipped from California. Partnered with Friends of the Library since 2010. N° de réf. du vendeur 1LAUHV002IR9
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Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
Etat : New. N° de réf. du vendeur ABLIING23Mar2317530032078
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Vendeur : Mispah books, Redhill, SURRE, Royaume-Uni
Hardcover. Etat : Very Good. Dust Jacket may NOT BE INCLUDED.CDs may be missing. book. N° de réf. du vendeur ERICA82708983830053
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Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors. 228 pp. Englisch. N° de réf. du vendeur 9780898383003
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Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Etat : New. In. N° de réf. du vendeur ria9780898383003_new
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Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Buch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors. N° de réf. du vendeur 9780898383003
Quantité disponible : 1 disponible(s)
Vendeur : THE SAINT BOOKSTORE, Southport, Royaume-Uni
Hardback. Etat : New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 528. N° de réf. du vendeur C9780898383003
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