Verilog HDL Synthesis, A Practical Primer - Couverture souple

Bhasker, J

Couverture souple

ISBN 10 : 098462922X ISBN 13 : 9780984629220

Editeur : Star Galaxy Publishing, 2018

Synopsis

With this book, you can: - Start writing synthesizable Verilog models quickly. - See what constructs are supported for synthesis and how these map to hardware so that you can get the desired logic. - Learn techniques to help avoid having functional mismatches. - Immediately start using many of the models for commonly used hardware elements described for your own use or modify these for your own application.

A propos du livre

À propos de l?auteur

J. Bhasker is the chair of the IEEE PAR 1364.1 Verilog Synthesis Interoperability Working Group that is working towards standardizing a Verilog subset for RTL synthesis. He is one of the main architects of the ArchSyn synthesis system developed at Bell Labs. He has taught Verilog HDL and Verilog HDL synthesis to many AT&T/Lucent designers. He is also the author of the bestselling book "A Verilog HDL Primer".

Détails de l'édition

• Éditeur: Star Galaxy Publishing
• Date d'édition: 2018
• Langue: anglais
• ISBN 10: 098462922X
• ISBN 13: 9780984629220
• Reliure: Broché
• Numéro d'édition: 1
• Nombre de pages: 236
• Coordonnées du fabricant: non disponible
• Personne responsable: non disponible