Articles liés à Power-Constrained Testing of Vlsi Circuits
Synopsis
Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.
Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.
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Power-Constrained Testing of VLSI Circuits (Frontiers in Electronic Testing)
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Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing) Nicolici, Nicola and Al-Hashimi, Bashir M.
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Power-Constrained Testing of VLSI Circuits
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Gebunden. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for redu. N° de réf. du vendeur 4094936
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Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing, 22B)
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Power-Constrained Testing of VLSI Circuits
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Springer US, Springer US Feb 2003, 2003
ISBN 10 : 140207235X
ISBN 13 : 9781402072352
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Buch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 192 pp. Englisch. N° de réf. du vendeur 9781402072352
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Power-Constrained Testing of VLSI Circuits : A Guide to the IEEE 1149.4 Test Standard
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Springer US, Springer New York, 2003
ISBN 10 : 140207235X
ISBN 13 : 9781402072352
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Buch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented. N° de réf. du vendeur 9781402072352
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Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard
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Springer-Verlag New York Inc., 2003
ISBN 10 : 140207235X
ISBN 13 : 9781402072352
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Hardback. Etat : New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 1020. N° de réf. du vendeur C9781402072352
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Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing, 22B)
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
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Etat : New. N° de réf. du vendeur ABLIING23Mar2411530144564
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Power-Constrained Testing of VLSI Circuits
Edité par
Springer US Feb 2003, 2003
ISBN 10 : 140207235X
ISBN 13 : 9781402072352
Neuf
Couverture rigide
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
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Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths. 192 pp. Englisch. N° de réf. du vendeur 9781402072352
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