Articles liés à Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Synopsis
This book is essential to understand new test methodologies, algorithms and industrial practices. Without its insight into the physics of nano-metric technologies, it would be difficult to develop system-level test strategies that yield a high IC fault coverage. The work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. The 2nd edition of Defect Oriented Testing has been extensively updated with the addition of chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering to provide a link between defect sources and yield. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
Acheter neuf
Afficher cet article
EUR 159,99
EUR 4,62 expédition depuis Royaume-Uni vers France
Destinations, frais et délaisAutres éditions populaires du même titre
Résultats de recherche pour Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Image d'archives
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing, 34)
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. In. N° de réf. du vendeur ria9781441942852_new
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
impression à la demandeVendeur : moluna, Greven, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Wide coverage of topics in test engineeringUnique defect-oriented focus of the materialsIntroduction to yield engineering common practicesThe 2nd edition of defect oriented testing has been extensively updated. New cha. N° de réf. du vendeur 4174637
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
impression à la demandeVendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance. 352 pp. Englisch. N° de réf. du vendeur 9781441942852
Quantité disponible : 2 disponible(s)
Image fournie par le vendeur
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Edité par
Springer US, Springer New York, 2010
ISBN 10 : 1441942858
ISBN 13 : 9781441942852
Neuf
Taschenbuch
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent. N° de réf. du vendeur 9781441942852
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Edité par
Springer US, Springer New York Nov 2010, 2010
ISBN 10 : 1441942858
ISBN 13 : 9781441942852
Neuf
Taschenbuch
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 352 pp. Englisch. N° de réf. du vendeur 9781441942852
Quantité disponible : 1 disponible(s)
Image d'archives
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing, 34)
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur ABLIING23Mar2411530295755
Quantité disponible : Plus de 20 disponibles
Image d'archives
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Vendeur : Revaluation Books, Exeter, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Paperback. Etat : Brand New. 2nd edition. 349 pages. 9.10x6.10x0.90 inches. In Stock. N° de réf. du vendeur x-1441942858
Quantité disponible : 2 disponible(s)