SystemVerilog for Verification: A Guide to Learning the Testbench Language Features - Couverture souple

Spear, Chris B.

Couverture souple

ISBN 10 : 144194561X ISBN 13 : 9781441945617

Editeur : Springer, 2010

Synopsis

The updated and expanded second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog 3.0 topics such as interfaces and data types. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch. This edition also includes a new chapter that covers "Interfacing to C" and many new and improved examples and explanations.

A propos du livre

Présentation de l'éditeur

This expanded book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. It contains a new chapter covering programs and interfaces as well as chapters with updated information.

Détails de l'édition

• Éditeur: Springer
• Date d'édition: 2010
• Langue: anglais
• ISBN 10: 144194561X
• ISBN 13: 9781441945617
• Reliure: Broché
• Numéro d'édition: 2
• Nombre de pages: 468
• Coordonnées du fabricant: non disponible
• Personne responsable: CMN Printpool Inh. Mathis Neumann; https://www.also.com/ec/cms5/en_6000/6000/index.jsp; ; Friedrich-Karl-Str. 9; Hamburg; Allemagne