Articles liés à Power-Constrained Testing of VLSI Circuits: A Guide...
Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard - Couverture souple
Synopsis
Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.
Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
Acheter neuf
Afficher cet article
EUR 92,27
EUR 9,70 expédition depuis Allemagne vers France
Destinations, frais et délais
Résultats de recherche pour Power-Constrained Testing of VLSI Circuits: A Guide...
Image fournie par le vendeur
Power-Constrained Testing of VLSI Circuits
impression à la demandeVendeur : moluna, Greven, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for redu. N° de réf. du vendeur 4175638
Quantité disponible : Plus de 20 disponibles
Image d'archives
Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing)
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. In. N° de réf. du vendeur ria9781441953155_new
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Power-Constrained Testing of VLSI Circuits
Edité par
Springer US, Springer US Dez 2010, 2010
ISBN 10 : 1441953159
ISBN 13 : 9781441953155
Neuf
Taschenbuch
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 192 pp. Englisch. N° de réf. du vendeur 9781441953155
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
Power-Constrained Testing of VLSI Circuits : A Guide to the IEEE 1149.4 Test Standard
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented. N° de réf. du vendeur 9781441953155
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
Power-constrained Testing of Vlsi Circuits
Vendeur : GreatBookPricesUK, Woodford Green, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur 11872075-n
Quantité disponible : Plus de 20 disponibles
Image d'archives
Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard
Edité par
Springer-Verlag New York Inc., 2010
ISBN 10 : 1441953159
ISBN 13 : 9781441953155
Neuf
Paperback / softback
Vendeur : THE SAINT BOOKSTORE, Southport, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Paperback / softback. Etat : New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 329. N° de réf. du vendeur C9781441953155
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Power-constrained Testing of Vlsi Circuits
Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur 11872075-n
Quantité disponible : Plus de 20 disponibles
Image d'archives
Power-Constrained Testing of VLSI Circuits
Vendeur : Books Puddle, New York, NY, Etats-Unis
Évaluation du vendeur 4 sur 5 étoiles
Etat : New. pp. 192. N° de réf. du vendeur 2614419236
Quantité disponible : 4 disponible(s)
Image d'archives
Power-Constrained Testing of VLSI Circuits
impression à la demandeVendeur : Majestic Books, Hounslow, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. Print on Demand pp. 192 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam. N° de réf. du vendeur 11254523
Quantité disponible : 4 disponible(s)
Image d'archives
Power-constrained Testing of Vlsi Circuits
Vendeur : Revaluation Books, Exeter, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Paperback. Etat : Brand New. 180 pages. 9.25x6.10x0.44 inches. In Stock. N° de réf. du vendeur x-1441953159
Quantité disponible : 2 disponible(s)