Articles liés à Digital Timing Macromodeling for VLSI Design Verification
- ÉditeurSpringer
- Date d'édition2012
- ISBN 10 1461359821
- ISBN 13 9781461359821
- ReliureBroché
- Langueanglais
- Nombre de pages292
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Digital Timing Macromodeling for VLSI Design Verification
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
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Taschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. N° de réf. du vendeur 9781461359821
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Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science)
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Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science)
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Digital Timing Macromodeling for VLSI Design Verification
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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timi. N° de réf. du vendeur 4194192
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Digital Timing Macromodeling for VLSI Design Verification
impression à la demandeVendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. 292 pp. Englisch. N° de réf. du vendeur 9781461359821
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Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science, 319)
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Springer, 2012
ISBN 10 : 1461359821
ISBN 13 : 9781461359821
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Paperback. Etat : Like New. Like New. book. N° de réf. du vendeur ERICA80014613598216
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