Articles liés à Power Aware Computing
Synopsis
List of Figures. List of Tables. Preface. Part I: 1. Comparative Analysis of Flip-Flops and Application of Data-Gating in Dynamic Flip-Flops for High Speed, Low Active and Low Leakage Power Dissipation; V. Srikantam, M. Martinez. 2. Low Power Sandwich/Spin Tunneling Memory Device; J. Daughton, et al. Part II: 3. Power-Efficient Issue Queue Design; A. Buyuktosunoglu, et al. 4. Micro-architecture Design and Control Speculation for Energy Reduction; D. Grunwald. 5. Energy-Exposed Instruction Sets; K. Asanovic, et al. Part III: 6. Dynamic Management of Power Consumption; T. Simunic. 7. Power Management Points in Power-Aware Real-Time Systems; R. Melhem, et al. 8. A Power-Aware API for Embedded and Portable Systems; C. Pereira, et al. Part IV: 9. PACT HDL: A Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations; A. Jones, et al. 10. Compiler Optimizations for Low Power Systems; M. Kandemir, et al. 11. Power-Performance Trade-Offs in Second Level Memory Used by an ARM-like RISC Architecture; K. Puttaswamy, et al. Part V: 12. Application-Level Power Awareness; J.A. Barnett. 13. A Power-Aware, Satellite-Based Parallel Signal Processing Scheme; P.M. Shriver, et al. 14. The Case for Power Management in Web Servers; P. Bohrer, et al. Part VI: 15. Et2: A Metric for Time and Energy Efficiency of Computation; A.J. Martin, et al. 16. Challenges for Architectural Level Power Modeling; Nam Sung Kim, et al. 17. Software Energy Profiling; A. Sinha, A. Chandrakasan. Index.
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