Logic Synthesis and Verification Algorithms - Couverture souple

Hachtel, Gary D. D.; Somenzi, Fabio

Couverture souple

ISBN 10 : 1475770367 ISBN 13 : 9781475770360

Editeur : Springer, 2013

Synopsis

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

Détails de l'édition

• Éditeur: Springer
• Date d'édition: 2013
• Langue: anglais
• ISBN 10: 1475770367
• ISBN 13: 9781475770360
• Reliure: Broché
• Nombre de pages: 600
• Coordonnées du fabricant: non disponible
• Personne responsable: CMN Printpool Inh. Mathis Neumann; https://www.also.com/ec/cms5/en_6000/6000/index.jsp; ; Friedrich-Karl-Str. 9; Hamburg; Allemagne