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Synopsis
Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods
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À propos de l?auteur
About the Author Dr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. Dr. Navabi's involvement with hardware description languages begins in 1976, when he started the development of a register-transfer level simulator for one of the very first HDLs. In 1981 he completed the development of a synthesis tool that generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages. He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL courses at Northeastern University in 1990. Since then he has conducted many short courses and tutorials on this subject in the United States and abroad. In addition to being a professor, he is also a consultant to CAE companies. Dr. Navabi received his M.S. and Ph.D. from the University of Arizona in 1978 and 1891, and his B.S. from the University of Texas at Austin in 1975. He is a senior member of IEEE, a member of IEEE Computer Society, member of ASEE, and ACM.
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Digital System Test and Testable Design : Using HDL Models and Architectures
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Springer US, 2016
ISBN 10 : 1489979271
ISBN 13 : 9781489979278
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Digital System Test and Testable Design
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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. About the AuthorDr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. N° de réf. du vendeur 385695968
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Digital System Test and Testable Design: Using HDL Models and Architectures
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Digital System Test and Testable Design : Using HDL Models and Architectures
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Digital System Test and Testable Design
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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms.Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies. 460 pp. Englisch. N° de réf. du vendeur 9781489979278
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Digital System Test and Testable Design
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Springer US, Springer US Aug 2016, 2016
ISBN 10 : 1489979271
ISBN 13 : 9781489979278
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Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
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Taschenbuch. Etat : Neu. Neuware -This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms.Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 460 pp. Englisch. N° de réf. du vendeur 9781489979278
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Digital System Test and Testable Design : Using HDL Models and Architectures
Edité par
Springer US, Springer US, 2016
ISBN 10 : 1489979271
ISBN 13 : 9781489979278
Neuf
Taschenbuch
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
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Taschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms.Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies. N° de réf. du vendeur 9781489979278
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Navabi:Digital System Test and Testable (eng)
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Digital System Test and Testable Design: Using HDL Models and Architectures
Edité par
Springer-Verlag New York Inc., 2016
ISBN 10 : 1489979271
ISBN 13 : 9781489979278
Neuf
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Vendeur : THE SAINT BOOKSTORE, Southport, Royaume-Uni
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Digital System Test and Testable Design: Using HDL Models and Architectures
Vendeur : Revaluation Books, Exeter, Royaume-Uni
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Paperback. Etat : Brand New. reprint edition. 435 pages. 10.00x7.01x1.04 inches. In Stock. N° de réf. du vendeur x-1489979271
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