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Synopsis
New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.
SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.
This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:
- modeling of bugs and defects;
- stimulus generation for validation and test purposes (including timing errors;
- design for testability.
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À propos de l?auteur
Matteo Sonza Reorda is the leader of the computer-aided design group of the Dipartimento di Automatica e Informatica, Politecnico di Torino. Zebo Peng is Professor of the chair in Computer Systems and Director of the Embedded Systems Laboratory at Linköping University.
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System-level Test and Validation of Hardware/Software Systems
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ISBN 13 : 9781849969536
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Kartoniert / Broschiert. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. The reader will learn about the state of the art in system-level validation and test procedures which will enhance both the reliability and performance of system on chip designsMatteo Sonza Reorda is the leader of the computer-aided design gro. N° de réf. du vendeur 4289006
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System-level Test and Validation of Hardware/Software Systems (Springer Series in Advanced Microelectronics, 17)
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System-level Test and Validation of Hardware/Software Systems
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ISBN 13 : 9781849969536
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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:modeling of bugs and defects;stimulus generation for validation and test purposes (including timing errors;design for testability. 192 pp. Englisch. N° de réf. du vendeur 9781849969536
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System-level Test and Validation of Hardware/Software Systems
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Taschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:modeling of bugs and defects;stimulus generation for validation and test purposes (including timing errors;design for testability. N° de réf. du vendeur 9781849969536
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System-level Test and Validation of Hardware/Software Systems
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Springer London, Springer London Nov 2010, 2010
ISBN 10 : 1849969531
ISBN 13 : 9781849969536
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Taschenbuch. Etat : Neu. Neuware -New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:modeling of bugs and defects;stimulus generation for validation and test purposes (including timing errors;design for testability.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 192 pp. Englisch. N° de réf. du vendeur 9781849969536
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System-level Test and Validation of Hardware/Software Systems
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System-level Test and Validation of Hardware/Software Systems
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