Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling: From the Clock Path to the Data Path - Couverture souple
Synopsis
PREFACE
ABOUT THE AUTHORS
ACKNOWLEDGEMENTS
1. INTRODUCTION
2. RECONFIGURABLE MICROARCHITECTURES DOWN TO PIPESTAGE AND MEMORY BANK LEVEL
3. AUTOMATED DESIGN FLOW AND RUN-TIME OPTIMIZATION FOR RECONFIGURABLE MICROARCHITECTURES
4. CASE STUDIES OF RECONFIGURABLE MICROARCHITECTURES: ACCELERATORS, MICROPROCESSOR AND MEMORIES
5. RECONFIGURABLE CLOCK NETWORKS, AUTOMATED DESIGN FLOWS, RUN-TIME OPTIMIZATION AND CASE STUDY
6. CONCLUSIONS
APPENDIX
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
