A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof - Couverture souple

Lutsyk, Petro; Oberhauser, Jonas; Paul, Wolfgang J.

Couverture souple

ISBN 10 : 3030432424 ISBN 13 : 9783030432423

Editeur : Springer, 2020

Synopsis

This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

- MIPS instruction set architecture (ISA) for application and for system programming

- cache coherent memory system

- store buffers in front of the data caches

- interrupts and exceptions

- memory management units (MMUs)

- pipelined processors: the classical five-stage pipeline is extended by two pipeline

stages for address translation

- local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

- I/O-interrupt controller and a disk

Détails de l'édition

• Éditeur: Springer
• Date d'édition: 2020
• Langue: anglais
• ISBN 10: 3030432424
• ISBN 13: 9783030432423
• Reliure: Broché
• Nombre de pages: 644
• Coordonnées du fabricant: ProductSafety@springernature.com; ProductSafety@springernature.com; ; Poststr. 9; Darmstadt; 64293; Allemagne