A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof - Couverture souple

Kovalev, Mikhail; Müller, Silvia M.; Paul, Wolfgang J.

 
9783319139050: A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof
Couverture souple
ISBN 10 : 3319139053 ISBN 13 : 9783319139050
Editeur : Springer, 2014

Synopsis

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.

The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.

Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Éditeur
Springer
Date d'édition
2014
Langue
anglais
ISBN 10 
3319139053
ISBN 13 
9783319139050
Reliure
Broché
Nombre de pages
364
Coordonnées du fabricant
non disponible
Personne responsable
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Autres éditions populaires du même titre

9783319139074: A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof

Edition présentée

ISBN 10 :  331913907X ISBN 13 :  9783319139074
Editeur : Springer, 2014
Couverture souple