Articles liés à System Level ESD Protection
Synopsis
This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
À propos de l?auteur
Dr. Vladislav Vashchenko is Director of ESD group at Maxim Integrated Corp responsible for major ESD development aspects across the entire $2.4B enterprise. During previous decade he was leading the ESD group at National Semiconductor Corp. and the decade till then he was a key contributor in reliability department of SRI "Pulsar"(Moscow). He received MS, Engineer-Physicist and "Ph.D. in Physics of Semiconductors" from Moscow Institute of Physics and Technology (1990) and "Doctor of Science in Microelectronics" degree (1997). He is author of over 140 U.S. patents and over 100 papers in the field, co-author of books "Physical Limitation of Semiconductor Devices" (2008) and "ESD Design for Analog Circuits" (2010, ).
Mirko Scholz received the degree "Diplomingenieur (FH)" from the University of Applied Sciences in Zwickau (Germany) in 2005 and the PhD degree in Electrical Engineering from the Vrije Universiteit in Brussels (VUB) in 2013. In April 2005 he joined the imec ESD team as ESD researcher where he authored and coauthored more than 70 publications, tutorials and patents in the field of ESD reliability and ESD testing. Since 2007, he has been a member of the Device Testing Working Groups of the ESDA standards committee where he currently chairs working group 5.6 (Human Metal Model).
Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.
Acheter neuf
Afficher cet article
EUR 85,27
EUR 3,45 expédition vers Etats-Unis
Destinations, frais et délais
Résultats de recherche pour System Level ESD Protection
Image d'archives
System Level ESD Protection
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur ABLIING23Mar3113020094156
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
System Level Esd Protection
Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur 27469078-n
Quantité disponible : 15 disponible(s)
Image d'archives
System Level ESD Protection
Vendeur : California Books, Miami, FL, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur I-9783319348926
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
System Level Esd Protection
Edité par
Springer, 2016
ISBN 10 : 3319348922
ISBN 13 : 9783319348926
Ancien ou d'occasion
Couverture souple
Vendeur : GreatBookPrices, Columbia, MD, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : As New. Unread book in perfect condition. N° de réf. du vendeur 27469078
Quantité disponible : 15 disponible(s)
Image d'archives
System Level ESD Protection (Paperback)
Edité par
Springer International Publishing AG, Cham, 2016
ISBN 10 : 3319348922
ISBN 13 : 9783319348926
Neuf
Paperback
Vendeur : Grand Eagle Retail, Bensenville, IL, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Paperback. Etat : new. Paperback. This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations. This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. N° de réf. du vendeur 9783319348926
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
System Level ESD Protection
ISBN 10 : 3319348922
ISBN 13 : 9783319348926
Neuf
Taschenbuch
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations. 340 pp. Englisch. N° de réf. du vendeur 9783319348926
Quantité disponible : 2 disponible(s)
Image fournie par le vendeur
System Level ESD Protection
Edité par
Springer International Publishing, 2016
ISBN 10 : 3319348922
ISBN 13 : 9783319348926
Neuf
Couverture souple
Vendeur : moluna, Greven, Allemagne
Évaluation du vendeur 4 sur 5 étoiles
Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides a systematic approach to on-chip ESD protection for system-level IC pinsDescribes a system-level co-design methodology, which uses external system level ESD protection components, together with on-chip ESD protection structureInclu. N° de réf. du vendeur 448746404
Quantité disponible : Plus de 20 disponibles
Image d'archives
System Level ESD Protection
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. In. N° de réf. du vendeur ria9783319348926_new
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
System Level ESD Protection
ISBN 10 : 3319348922
ISBN 13 : 9783319348926
Neuf
Taschenbuch
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. Neuware -This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 340 pp. Englisch. N° de réf. du vendeur 9783319348926
Quantité disponible : 2 disponible(s)
Image fournie par le vendeur
System Level ESD Protection
Edité par
Springer International Publishing, Springer Nature Switzerland, 2016
ISBN 10 : 3319348922
ISBN 13 : 9783319348926
Neuf
Taschenbuch
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations. N° de réf. du vendeur 9783319348926
Quantité disponible : 1 disponible(s)