Articles liés à ASIC/SoC Functional Design Verification
Synopsis
This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, ReuseMethodology from Algorithm/ESL to RTL, and other overall methodologies.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
À propos de l?auteur
Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium Architecture Verification team) and after a route of couple of startups, worked at Applied Micro and currently at TSMC.
He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs. At TSMC he architected and went into production with two industry standard TSMC ESL Reference Flows that take designs from ESL to RTL while preserving the verification environment for reuse from ESL to RTL.
He holds 14 U.S. Patents in the field of SoC and 3DIC design verification.
He is also the author of Second Edition of the book "SystemVerilog Assertions and FunctionalCoverage - A comprehensive guide to languages, methodologies and applications". Springer (June 2016).
Ashok earned an MSEE from University of Missouri.
In his spare time, he is an amateur photographer and likes to play drums on 70's rock music driving his neighbors up the wall J
Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.
- ÉditeurSpringer
- Date d'édition2017
- ISBN 10 3319594176
- ISBN 13 9783319594170
- ReliureRelié
- Langueanglais
- Numéro d'édition1
- Nombre de pages360
- Coordonnées du fabricantnon disponible
Acheter neuf
Afficher cet article
EUR 146,12
EUR 9,70 expédition depuis Allemagne vers France
Destinations, frais et délaisAutres éditions populaires du même titre
Résultats de recherche pour ASIC/SoC Functional Design Verification
Image fournie par le vendeur
ASIC/SoC Functional Design Verification
Edité par
Springer International Publishing, 2017
ISBN 10 : 3319594176
ISBN 13 : 9783319594170
Neuf
Couverture rigide
Vendeur : moluna, Greven, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Gebunden. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides readers with a single-source guide to the entire domain of functional design verificationDescribe many industry standard tools available in the market so readers know which tools to pursue to their greatest advantageIncludes. N° de réf. du vendeur 151045675
Quantité disponible : Plus de 20 disponibles
Image d'archives
ASIC/SoC Functional Design Verification
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. In English. N° de réf. du vendeur ria9783319594170_new
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
ASIC/SoC Functional Design Verification : A Comprehensive Guide to Technologies and Methodologies
Edité par
Springer International Publishing, Springer Nature Switzerland, 2017
ISBN 10 : 3319594176
ISBN 13 : 9783319594170
Neuf
Couverture rigide
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Buch. Etat : Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, ReuseMethodology from Algorithm/ESL to RTL, and other overall methodologies. N° de réf. du vendeur 9783319594170
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
ASIC/SoC Functional Design Verification
ISBN 10 : 3319594176
ISBN 13 : 9783319594170
Neuf
Couverture rigide
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Buch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, ReuseMethodology from Algorithm/ESL to RTL, and other overall methodologies. 360 pp. Englisch. N° de réf. du vendeur 9783319594170
Quantité disponible : 2 disponible(s)
Image fournie par le vendeur
ASIC/SoC Functional Design Verification
ISBN 10 : 3319594176
ISBN 13 : 9783319594170
Neuf
Couverture rigide
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Buch. Etat : Neu. Neuware -This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, ReuseMethodology from Algorithm/ESL to RTL, and other overall methodologies.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 360 pp. Englisch. N° de réf. du vendeur 9783319594170
Quantité disponible : 2 disponible(s)
Image d'archives
ASIC/SoC Functional Design Verification
Vendeur : California Books, Miami, FL, Etats-Unis
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. N° de réf. du vendeur I-9783319594170
Quantité disponible : Plus de 20 disponibles
Image d'archives
ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies
Vendeur : Books Puddle, New York, NY, Etats-Unis
Évaluation du vendeur 4 sur 5 étoiles
Etat : New. pp. 239. N° de réf. du vendeur 26375270289
Quantité disponible : 4 disponible(s)
Image d'archives
ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies
impression à la demandeVendeur : Biblios, Frankfurt am main, HESSE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. PRINT ON DEMAND pp. 239. N° de réf. du vendeur 18375270299
Quantité disponible : 4 disponible(s)
Image d'archives
ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies
impression à la demandeVendeur : Majestic Books, Hounslow, Royaume-Uni
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. Print on Demand pp. 239. N° de réf. du vendeur 371823694
Quantité disponible : 4 disponible(s)
Image d'archives
ASIC/SoC Functional Design Verification
Vendeur : Mispah books, Redhill, SURRE, Royaume-Uni
Évaluation du vendeur 4 sur 5 étoiles
Hardcover. Etat : New. New. book. N° de réf. du vendeur ERICA77333195941766
Quantité disponible : 1 disponible(s)