This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
Sven Goossens received his M.Sc. in Embedded Systems from the Eindhoven University of Technology in 2010. He worked as a researcher in the Electrical Engineering of the same university until 2011, and then started as a Ph.D. student, graduating in 2015. He is currently employed as a Hardware Architect at Intrinsic-ID. His research interests include mixed time-criticality systems, composability and SDRAM controllers.
Karthik Chandrasekar earned his M.Sc. degree in Computer Engineering from TU Delft in the Netherlands in November 2009. In October 2014, he received his Ph.D. also from the same university. His research interests include SoC Architectures, DRAM memories & memory controllers, on-chip communication networks and performance & power modeling and analysis. He is currently employed as a Senior Architect at Nvidia.Benny Akesson received his M.Sc. degree at Lund Institute of Technology, Sweden in 2005 and a Ph.D. from Eindhoven University of Technology, the Netherlands in 2010. Since then, he has been employed as a Researcher at Eindhoven University of Technology, Czech Technical University in Prague, and CISTER/INESC TEC Research Unit in Porto. Currently, he is working as a Research Fellow at TNO-ESI. His research interests include memory controller architectures, real-time scheduling, performance modeling, and performance virtualization. He has published more than 50 peer-reviewed conference papers and journal articles, as well as two books about memory controllers for real-time embedded systems.
Kees Goossens received his Ph.D. in Computer Science from the University of Edinburgh in 1993. He worked for Philips/NXP Research from 1995 to 2010 on networks-onchips for consumer electronics, where real-time performance, predictability, and costs are major constraints. He was part-time professor at Delft University from 2007 to 2010, and is now full professor at the Eindhoven University of Technology, where his research focuses on composable (virtualized), predictable (real-time), low-power embedded systems, supporting multiple models of computation. He published 4 books, 100+ papers, and 24 patents.
Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.
Vendeur : Lucky's Textbooks, Dallas, TX, Etats-Unis
Etat : New. N° de réf. du vendeur ABLIING23Mar3113020107297
Quantité disponible : Plus de 20 disponibles
Vendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Etat : New. In. N° de réf. du vendeur ria9783319811963_new
Quantité disponible : Plus de 20 disponibles
Vendeur : California Books, Miami, FL, Etats-Unis
Etat : New. N° de réf. du vendeur I-9783319811963
Quantité disponible : Plus de 20 disponibles
Vendeur : Chiron Media, Wallingford, Royaume-Uni
Paperback. Etat : New. N° de réf. du vendeur 6666-IUK-9783319811963
Quantité disponible : 10 disponible(s)
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template. 232 pp. Englisch. N° de réf. du vendeur 9783319811963
Quantité disponible : 2 disponible(s)
Vendeur : Kennys Bookshop and Art Galleries Ltd., Galway, GY, Irlande
Etat : New. 2018. Paperback. . . . . . N° de réf. du vendeur V9783319811963
Quantité disponible : 15 disponible(s)
Vendeur : moluna, Greven, Allemagne
Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Discusses power-constrained mixed-time-criticality systems and why they are complex to design and verify Explains the concepts of predictability and composability and how they address the design and verification challenges of mixed-time-criticali. N° de réf. du vendeur 448756098
Quantité disponible : Plus de 20 disponibles
Vendeur : preigu, Osnabrück, Allemagne
Taschenbuch. Etat : Neu. Memory Controllers for Mixed-Time-Criticality Systems | Architectures, Methodologies and Trade-offs | Sven Goossens (u. a.) | Taschenbuch | xxvii | Englisch | 2018 | Springer International Publishing | EAN 9783319811963 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. N° de réf. du vendeur 114236741
Quantité disponible : 5 disponible(s)
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Taschenbuch. Etat : Neu. Neuware -This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 232 pp. Englisch. N° de réf. du vendeur 9783319811963
Quantité disponible : 2 disponible(s)
Vendeur : Kennys Bookstore, Olney, MD, Etats-Unis
Etat : New. 2018. Paperback. . . . . . Books ship from the US and Ireland. N° de réf. du vendeur V9783319811963
Quantité disponible : 15 disponible(s)