Articles liés à Instruction Dispatching Techniques for SMT Processors:...

Instruction Dispatching Techniques for SMT Processors: Efficient Instruction Queue sharing for SMT Processors - Couverture souple

Debnath, Monobrata; Lin, Wei-Ming

 
9783330037090: Instruction Dispatching Techniques for SMT Processors: Efficient Instruction Queue sharing for SMT Processors
Couverture souple
ISBN 10 : 3330037091 ISBN 13 : 9783330037090
Editeur : LAP LAMBERT Academic Publishing, 2017

Synopsis

Simultaneous Multi-Threading (SMT) provides an improved technique to enhance resource utilization ability by sharing key data path components among multiple independent threads. When critical resources are shared by multiple threads, effective use of these resources proves to be the most important factor in fully exploiting the system potential. The thread-level parallelism (TLP) present among the threads can be exploited intelligently to compensate the limited instruction level parallelism available among threads. The efficient of sharing of Instruction Queue (IQ) among multiple threads plays a crucial role on the overall system performance. In this book, we discuss the techniques to enhance the usability of IQ to further improve the overall performance.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Simultaneous Multi-Threading (SMT) provides an improved technique to enhance resource utilization ability by sharing key data path components among multiple independent threads. When critical resources are shared by multiple threads, effective use of these resources proves to be the most important factor in fully exploiting the system potential. The thread-level parallelism (TLP) present among the threads can be exploited intelligently to compensate the limited instruction level parallelism available among threads. The efficient of sharing of Instruction Queue (IQ) among multiple threads plays a crucial role on the overall system performance. In this book, we discuss the techniques to enhance the usability of IQ to further improve the overall performance.

Biographie de l'auteur

Monobrata Debnath received his M.S. in Computer Engineering and Ph.D. in Electrical Engineering in the year 2010 and 2016 respectively from the University Of Texas at San Antonio, where he is currently working as a research scientist. His research interests include computer architecture, networks-on-chip, IoT and Simultaneous Multi-threading.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2017
Langue
anglais
ISBN 10 
3330037091
ISBN 13 
9783330037090
Reliure
Broché
Nombre de pages
56
Coordonnées du fabricant
non disponible
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