Parallel Inverse Halftoning via Look-Up Table (LUT) Partitioning: Methods to Parallelize the LUT Inverse Halftoning with Minimum Additional Memory Requirements and Comparable Image Quality - Couverture souple

Sait, Sadiq M.

 
9783639055252: Parallel Inverse Halftoning via Look-Up Table (LUT) Partitioning: Methods to Parallelize the LUT Inverse Halftoning with Minimum Additional Memory Requirements and Comparable Image Quality
Couverture souple
ISBN 10 : 363905525X ISBN 13 : 9783639055252
Editeur : VDM Verlag Dr. Müller, 2009

Synopsis

The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this book we propose six algorithms to parallelize the LUT method so that more pixels can be concurrently inverse halftone using minimum additional hardware. The proposed algorithms partition the single LUT of serial LUT method into N smaller Look-Up Tables (s- LUTs) such that the total number of contents in all s-LUTs remain equal to the number of contents in the single LUT of serial LUT method. The proposed parallel algorithms have image quality equal to the serial LUT method when gain in clock cycles over the serial method is less and have lesser image quality comparetively to serial LUT method when gain in clock cycles over the serial method is very high. The parallel algorithms can be implemented on FPGA (Field Programmable Gate Arrays) devices with external CAM (Content Addressable Memories) and ROM (Read Only Memories)

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Présentation de l'éditeur

The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this book we propose six algorithms to parallelize the LUT method so that more pixels can be concurrently inverse halftone using minimum additional hardware. The proposed algorithms partition the single LUT of serial LUT method into N smaller Look-Up Tables (s- LUTs) such that the total number of contents in all s-LUTs remain equal to the number of contents in the single LUT of serial LUT method. The proposed parallel algorithms have image quality equal to the serial LUT method when gain in clock cycles over the serial method is less and have lesser image quality comparetively to serial LUT method when gain in clock cycles over the serial method is very high. The parallel algorithms can be implemented on FPGA (Field Programmable Gate Arrays) devices with external CAM (Content Addressable Memories) and ROM (Read Only Memories)

Biographie de l'auteur

Sadiq M. Sait:(BS'81,MS'83,PhD'87) is a Professor of Computer Engineering at KFUPM, Dhahran. He has authored over 100 research papers in Intl Journals & Conferences and several books on VLSI Design Automation and Iterative Algorithms. Umair F. Siddiqi: (BE'02,MS'07) is Applications Developer at KFUPM. He has 4 papers in Intl Journals & Confs.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
VDM Verlag Dr. Müller
Date d'édition
2009
Langue
anglais
ISBN 10 
363905525X
ISBN 13 
9783639055252
Reliure
Broché
Nombre de pages
120
Coordonnées du fabricant
non disponible
Personne responsable
non disponible