SEARCHLESS IFS FRACTALIMAGE ENCODING: EFFICIENT SOFTWARE ALGORITHMS AND HARDWARE ARCHITECTURES - Couverture souple

Wu, Xianwei

 
9783639095692: SEARCHLESS IFS FRACTALIMAGE ENCODING: EFFICIENT SOFTWARE ALGORITHMS AND HARDWARE ARCHITECTURES
Couverture souple
ISBN 10 : 3639095693 ISBN 13 : 9783639095692
Editeur : VDM Verlag, 2009

Synopsis

Fractal image compression is a lossy technique with high compression ratios, good quality, and fast decoding. However, the computational complexity and long coding time makes it unpractical. This book introduces possible solutions for these problems. In the book, A full quadtree and a full binary-tree searchless fractal algorithms introduced in chapter 1 and 2. The full quadtree algorithm introduced in chapter 3 has a simpler data structure allowing a hardware implementation. The two-level quadtree algorithm introduced in chapter 4 is an improved version of chapter 3. Chapter 5 gives a two-level fractal FPGA hardware architecture design corresponding to chapter 3. Chapter 6 improves the result of chapter 5 by employing 4 quadtree levels. The most important findings of this book are: 1. The algorithms fix the location of domain block. It reduces the complexity of the fractal encoding. 2. The algorithms can encode smaller range blocks, even single pixels. This is unique among current fractal algorithm implementations. 3. The algorithms are faster than the traditional methods because of no domain block searching. 4. The algorithms can be transferred into FPGA hardware architecture.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Fractal image compression is a lossy technique with high compression ratios, good quality, and fast decoding. However, the computational complexity and long coding time makes it unpractical. This book introduces possible solutions for these problems. In the book, A full quadtree and a full binary-tree searchless fractal algorithms introduced in chapter 1 and 2. The full quadtree algorithm introduced in chapter 3 has a simpler data structure allowing a hardware implementation. The two-level quadtree algorithm introduced in chapter 4 is an improved version of chapter 3. Chapter 5 gives a two-level fractal FPGA hardware architecture design corresponding to chapter 3. Chapter 6 improves the result of chapter 5 by employing 4 quadtree levels. The most important findings of this book are: 1. The algorithms fix the location of domain block. It reduces the complexity of the fractal encoding. 2. The algorithms can encode smaller range blocks, even single pixels. This is unique among current fractal algorithm implementations. 3. The algorithms are faster than the traditional methods because of no domain block searching. 4. The algorithms can be transferred into FPGA hardware architecture.

Biographie de l'auteur

Xianwei Wu received the B.S. and M.S. in Electrical Engineering from Jilin University of Technology China in 1994 and 2002. He received the Ph.D. in ECE Department at the University of Alabama in 2006. His research interests include image processing, VHDL hardware design, microprocessor and micro-controller based design and embedded system design.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
VDM Verlag
Date d'édition
2009
Langue
anglais
ISBN 10 
3639095693
ISBN 13 
9783639095692
Reliure
Broché
Nombre de pages
140
Coordonnées du fabricant
non disponible
Personne responsable
non disponible