High Performance and Energy Efficient Many-core DSP Systems: An Asynchronous Array of Simple Processors - Couverture souple

Yu, Zhiyi

 
9783639098594: High Performance and Energy Efficient Many-core DSP Systems: An Asynchronous Array of Simple Processors
Couverture souple
ISBN 10 : 3639098595 ISBN 13 : 9783639098594
Editeur : VDM Verlag Dr. Müller, 2008

Synopsis

This book investigates the architecture design, physical implementation, result evaluation, and feature analysis of a many-core processor for DSP applications. The system is composed of a 2-D array of simple single-issue programmable processors interconnected by a reconfigurable mesh network, and processors operate completely asynchronously with respect to each other in a Globally Asynchronous Locally Synchronous fashion. The processor is called Asynchronous Array of simple Processors (AsAP). A 6×6 array has been fabricated in a 0.18 µm CMOS technology. The physical design concerns timing issues for robust implementations, and takes full advantages of their potential scalability. Each processor occupies 0.66 mm², is fully functional at a clock rate of 520¿540 MHz under 1.8 V, and dissipates 94 mW while the clock is 100% active. The system is also easily scalable, and is well- suited to future fabrication technologies.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

This book investigates the architecture design, physical implementation, result evaluation, and feature analysis of a many-core processor for DSP applications. The system is composed of a 2-D array of simple single-issue programmable processors interconnected by a reconfigurable mesh network, and processors operate completely asynchronously with respect to each other in a Globally Asynchronous Locally Synchronous fashion. The processor is called Asynchronous Array of simple Processors (AsAP). A 6×6 array has been fabricated in a 0.18 µm CMOS technology. The physical design concerns timing issues for robust implementations, and takes full advantages of their potential scalability. Each processor occupies 0.66 mm², is fully functional at a clock rate of 520¿540 MHz under 1.8 V, and dissipates 94 mW while the clock is 100% active. The system is also easily scalable, and is well- suited to future fabrication technologies.

Biographie de l'auteur

Zhiyi Yu received the Ph.D. degree from ECE Department of UC Davis in 2007. He is currently an Associate Professor with the Microelectronics Department, Fudan University, China. Bevan Baas received the Ph.D. degree from EE department of Stanford University in 1999. He is currently an Associate Professor with the ECE Department, UC Davis.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
VDM Verlag Dr. Müller
Date d'édition
2008
Langue
anglais
ISBN 10 
3639098595
ISBN 13 
9783639098594
Reliure
Broché
Nombre de pages
168
Coordonnées du fabricant
non disponible
Personne responsable
non disponible