Improving Performance and Reducing Power with Hardware Acceleration: Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow - Couverture souple

Ihrig, Colin J.

 
9783639106909: Improving Performance and Reducing Power with Hardware Acceleration: Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow
Couverture souple
ISBN 10 : 3639106903 ISBN 13 : 9783639106909
Editeur : VDM Verlag Dr. Müller, 2008

Synopsis

Modern electronic design automation tools can be used to apply a variety of transformations to hardware blocks in an effort to achieve performance and power savings. A number of such transformations require tools with intimate knowledge of the design's timing characteristics. Static timing analysis estimates the worst-case timing behavior of hardware data flow graphs. The static timing analyzer described in this book operates on data flow graphs which are generated as intermediate representations within a C to VHDL hardware acceleration compiler. Two additional tools were then developed which utilize the results of the static timing analysis. An automated pipelining tool was developed to increase the throughput of large blocks of combinational logic generated by the compiler. Another tool was designed to mitigate power consumption resulting from combinational glitching. By inserting special signal buffers with preselected propagation delays, known as delay elements, functional units can be kept inactive until their inputs stabilize. This book explores these tools as well as the various design tradeoffs resulting from their use.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Modern electronic design automation tools can be used to apply a variety of transformations to hardware blocks in an effort to achieve performance and power savings. A number of such transformations require tools with intimate knowledge of the design's timing characteristics. Static timing analysis estimates the worst-case timing behavior of hardware data flow graphs. The static timing analyzer described in this book operates on data flow graphs which are generated as intermediate representations within a C to VHDL hardware acceleration compiler. Two additional tools were then developed which utilize the results of the static timing analysis. An automated pipelining tool was developed to increase the throughput of large blocks of combinational logic generated by the compiler. Another tool was designed to mitigate power consumption resulting from combinational glitching. By inserting special signal buffers with preselected propagation delays, known as delay elements, functional units can be kept inactive until their inputs stabilize. This book explores these tools as well as the various design tradeoffs resulting from their use.

Biographie de l'auteur

Colin J. Ihrig received his B.S. and M.S. in 2005 and 2008 and is currently pursing his Ph.D. in CoE from the Univ. of Pittsburgh. Alex K. Jones received his B.S. in Physics in 1998 from William and Mary and his M.S. and Ph.D. in ECE from Northwestern Univ. in 2000 and 2002. He is currently a faculty member at the Univ. of Pittsburgh.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
VDM Verlag Dr. Müller
Date d'édition
2008
Langue
anglais
ISBN 10 
3639106903
ISBN 13 
9783639106909
Reliure
Broché
Nombre de pages
92
Coordonnées du fabricant
non disponible
Personne responsable
non disponible