Modern electronic design automation tools can be used to apply a variety of transformations to hardware blocks in an effort to achieve performance and power savings. A number of such transformations require tools with intimate knowledge of the design's timing characteristics. Static timing analysis estimates the worst-case timing behavior of hardware data flow graphs. The static timing analyzer described in this book operates on data flow graphs which are generated as intermediate representations within a C to VHDL hardware acceleration compiler. Two additional tools were then developed which utilize the results of the static timing analysis. An automated pipelining tool was developed to increase the throughput of large blocks of combinational logic generated by the compiler. Another tool was designed to mitigate power consumption resulting from combinational glitching. By inserting special signal buffers with preselected propagation delays, known as delay elements, functional units can be kept inactive until their inputs stabilize. This book explores these tools as well as the various design tradeoffs resulting from their use.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
Modern electronic design automation tools can be used to apply a variety of transformations to hardware blocks in an effort to achieve performance and power savings. A number of such transformations require tools with intimate knowledge of the design's timing characteristics. Static timing analysis estimates the worst-case timing behavior of hardware data flow graphs. The static timing analyzer described in this book operates on data flow graphs which are generated as intermediate representations within a C to VHDL hardware acceleration compiler. Two additional tools were then developed which utilize the results of the static timing analysis. An automated pipelining tool was developed to increase the throughput of large blocks of combinational logic generated by the compiler. Another tool was designed to mitigate power consumption resulting from combinational glitching. By inserting special signal buffers with preselected propagation delays, known as delay elements, functional units can be kept inactive until their inputs stabilize. This book explores these tools as well as the various design tradeoffs resulting from their use.
Colin J. Ihrig received his B.S. and M.S. in 2005 and 2008 and is currently pursing his Ph.D. in CoE from the Univ. of Pittsburgh. Alex K. Jones received his B.S. in Physics in 1998 from William and Mary and his M.S. and Ph.D. in ECE from Northwestern Univ. in 2000 and 2002. He is currently a faculty member at the Univ. of Pittsburgh.
Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.
EUR 29,80 expédition depuis Royaume-Uni vers France
Destinations, frais et délaisEUR 4,76 expédition depuis Royaume-Uni vers France
Destinations, frais et délaisVendeur : Ria Christie Collections, Uxbridge, Royaume-Uni
Etat : New. In. N° de réf. du vendeur ria9783639106909_new
Quantité disponible : Plus de 20 disponibles
Vendeur : PBShop.store US, Wood Dale, IL, Etats-Unis
PAP. Etat : New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. N° de réf. du vendeur L0-9783639106909
Quantité disponible : Plus de 20 disponibles
Vendeur : moluna, Greven, Allemagne
Kartoniert / Broschiert. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Modern electronic design automation tools can be used to apply a variety of transformations to hardware blocks in an effort to achieve performance and power savings. A number of such transformations require tools with intimate knowle. N° de réf. du vendeur 4958034
Quantité disponible : Plus de 20 disponibles
Vendeur : PBShop.store UK, Fairford, GLOS, Royaume-Uni
PAP. Etat : New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. N° de réf. du vendeur L0-9783639106909
Quantité disponible : Plus de 20 disponibles
Vendeur : Chiron Media, Wallingford, Royaume-Uni
Paperback. Etat : New. N° de réf. du vendeur 6666-IUK-9783639106909
Quantité disponible : 10 disponible(s)
Vendeur : California Books, Miami, FL, Etats-Unis
Etat : New. N° de réf. du vendeur I-9783639106909
Quantité disponible : Plus de 20 disponibles
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Modern electronic design automation tools can be used to apply a variety of transformations to hardware blocks in an effort to achieve performance and power savings. A number of such transformations require tools with intimate knowledge of the design's timing characteristics. Static timing analysis estimates the worst-case timing behavior of hardware data flow graphs. The static timing analyzer described in this book operates on data flow graphs which are generated as intermediate representations within a C to VHDL hardware acceleration compiler. Two additional tools were then developed which utilize the results of the static timing analysis. An automated pipelining tool was developed to increase the throughput of large blocks of combinational logic generated by the compiler. Another tool was designed to mitigate power consumption resulting from combinational glitching. By inserting special signal buffers with preselected propagation delays, known as delay elements, functional units can be kept inactive until their inputs stabilize. This book explores these tools as well as the various design tradeoffs resulting from their use. N° de réf. du vendeur 9783639106909
Quantité disponible : 2 disponible(s)
Vendeur : Mispah books, Redhill, SURRE, Royaume-Uni
Paperback. Etat : Like New. Like New. book. N° de réf. du vendeur ERICA75836391069036
Quantité disponible : 1 disponible(s)