Data Integrity for On-Chip Interconnects: A Communication Theoretic Approach - Couverture souple

Singhal, Rohit

 
9783639203660: Data Integrity for On-Chip Interconnects: A Communication Theoretic Approach
Couverture souple
ISBN 10 : 3639203666 ISBN 13 : 9783639203660
Editeur : VDM Verlag, 2009

Synopsis

The desire for having a smaller-faster chip that does more than ever before, has led to shrinking feature size and growing integration density. This integration has left designers grappling with increasing concerns of signal-integrity (SI), timing- closure and power-consumption. Firstly, the shrinking feature size has resulted in greater delays. Further, the adjacent wires are now very close and cause Cross-talk to each other's signals. Traditional designs focus on protecting SI on long parallel wires. The SI designs accomodate the worst case delays of signals; while they aim to improve the worst-case delays at a circuit level using novel tricks, they are transparent to the actual data carried in the wires. Departing from this trend, this work aims to introduce an information theoretic approach to address data-integrity (DI). A novel approach for evaluating the data carrying capacity of long parallel wires is presented herein. This capacity is much greater than the data-rate achieved by SI designs. This work also proposes several practical designs with data-rate approaching this capacity.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

The desire for having a smaller-faster chip that does more than ever before, has led to shrinking feature size and growing integration density. This integration has left designers grappling with increasing concerns of signal-integrity (SI), timing- closure and power-consumption. Firstly, the shrinking feature size has resulted in greater delays. Further, the adjacent wires are now very close and cause Cross-talk to each other's signals. Traditional designs focus on protecting SI on long parallel wires. The SI designs accomodate the worst case delays of signals; while they aim to improve the worst-case delays at a circuit level using novel tricks, they are transparent to the actual data carried in the wires. Departing from this trend, this work aims to introduce an information theoretic approach to address data-integrity (DI). A novel approach for evaluating the data carrying capacity of long parallel wires is presented herein. This capacity is much greater than the data-rate achieved by SI designs. This work also proposes several practical designs with data-rate approaching this capacity.

Biographie de l'auteur

Dr. Singhal is a Senior Design Engineer, at Integrated Device Technology Inc. Dr. Choi and Dr. Mahapatra are both Associate Professors at Texas A&M University. This work resulted from Dr. Singhal's doctoral research performed under the guidance of Dr. Choi and Dr. Mahapatra at Texas A&M University.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
VDM Verlag
Date d'édition
2009
Langue
anglais
ISBN 10 
3639203666
ISBN 13 
9783639203660
Reliure
Broché
Nombre de pages
132
Coordonnées du fabricant
non disponible
Personne responsable
non disponible