FPGA Implementation of MPEG-2 Video decoder: FPGA Implementation of base layer MPEG-2 Video decoder - Couverture souple

Kumar, Jiwesh; Pandey, Pranjal

 
9783639295924: FPGA Implementation of MPEG-2 Video decoder: FPGA Implementation of base layer MPEG-2 Video decoder
Couverture souple
ISBN 10 : 3639295927 ISBN 13 : 9783639295924
Editeur : VDM Verlag Dr. Müller, 2010

Synopsis

The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 ?university program" board.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 ?university program" board.

Biographie de l'auteur

Jiwesh Kumar, B.Tech Electronics and Communication Engineering, NIT Bhopal, Systems Engineer at BrahMos Aerospace

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
VDM Verlag Dr. Müller
Date d'édition
2010
Langue
anglais
ISBN 10 
3639295927
ISBN 13 
9783639295924
Reliure
Broché
Nombre de pages
72
Coordonnées du fabricant
non disponible
Personne responsable
non disponible