Articles liés à Robotic Exploration and Landmark Determination: Hardware-Eff...

Robotic Exploration and Landmark Determination: Hardware-Efficient Algorithms and FPGA Implementations - Couverture souple

Sridharan, K.; Kumar, Panakala Rajesh

 
9783642094651: Robotic Exploration and Landmark Determination: Hardware-Efficient Algorithms and FPGA Implementations

Synopsis

This book presents hardware-efficient algorithms and FPGA implementations for two robotic tasks, namely exploration and landmark determination. The work identifies scenarios for mobile robotics where parallel processing and selective shutdown offered by FPGAs are invaluable. The book proceeds to systematically develop memory-driven VLSI architectures for both the tasks. The architectures are ported to a low-cost FPGA with a fairly small number of system gates.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

À propos de l'auteur

Professor K. Sridharan received his Ph.D. from Rensselaer Polytechnic Institute, Troy, NY, USA, in 1995. He was an Assistant Professor at the Indian Institute of Technology (IIT) Guwahati from 1996 to 2001. In June 2001, has moved to the IIT Madras, Chennai, India, where he is currently a Professor. He was a visiting staff member at Nanyang Technological University, Singapore, from 2000 to 2001 and from 2006 to 2008. Prof. Sridharan was the recipient of the 2009 Vikram Sarabhai Research Award and the 2011 Tan Chin Tuan Fellowship. He formerly served as an Associate Editor of the IEEE Transactions on Industrial Electronics. Dr. B. Srinivasu received his Ph.D. from the Department of Electrical Engineering, IIT Madras, in 2017. He was a Postdoctoral Research Fellow at the School of Computer Science and Engineering, Nanyang Technological University, from May 2017 to July 2019. He is currently an Assistant Professor at the School of Computing and Electrical Engineering, Indian Institute of Technology (IIT) Mandi. Dr. Vikramkumar Pudi received his Ph.D. from the Department of Electrical Engineering, IIT Madras, in 2014. He was a Postdoctoral Fellow at the University of British Columbia from 2014 to 2015 and a Research Fellow at Nanyang Technological University, Singapore, from 2015 to 2018. Since November 2018, he has been an Assistant Professor at the Indian Institute of Technology (IIT) Tirupati.

À propos de la quatrième de couverture

Much of the research effort in mobile robots in the recent past has been on sensing and design of time-efficient algorithms for tasks such as localization, mapping and navigation. Mobile robots typically employ an embedded computer for high level computations. As applications of robots expand, there is a need to investigate architecturally efficient choices for this embedded computing platform. In particular, it is valuable to process data to obtain time, space and energy-efficient solutions for various robotic tasks.

This book presents hardware-efficient algorithms and FPGA implementations for two robotic tasks, namely exploration and landmark determination. The work identifies scenarios for mobile robotics where parallel processing and selective shutdown offered by FPGAs are invaluable. The book proceeds to systematically develop memory-driven VLSI architectures for both the tasks. The architectures are ported to a low-cost FPGA with a fairly small number of system gates. A robot fabricated with this FPGA on-board serves to validate the efficacy of the approach. Numerous experiments with the robot are reported.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.