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High Performance Domino Logic Circuits in Low Power VLSI Design: A Novel Approach - Couverture souple
Synopsis
The advancement of CMOS technologies paved the road for a growing market of mobile and portable electronic devices. This growth is driven by the continual integration of complex analog and digital building blocks on a single chip, so silicon area and power consumption are the two most valued aspects of the design. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this dissertation, 2:1 multiplexer and 1:2 decoder is proposed. The proposed 2:1 multiplexer and 1:2 decoder design based on proposed high performance domino logic circuit are tested in 45nm and 65nm technologies to prove its technology independence. Design is also experimented under various substrate-biasing schemes and then the best substrate biasing technique is implemented. The proposed design is better in terms of power, delay and power delay product in comparison to other biasing conditions.
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Présentation de l'éditeur
The advancement of CMOS technologies paved the road for a growing market of mobile and portable electronic devices. This growth is driven by the continual integration of complex analog and digital building blocks on a single chip, so silicon area and power consumption are the two most valued aspects of the design. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this dissertation, 2:1 multiplexer and 1:2 decoder is proposed. The proposed 2:1 multiplexer and 1:2 decoder design based on proposed high performance domino logic circuit are tested in 45nm and 65nm technologies to prove its technology independence. Design is also experimented under various substrate-biasing schemes and then the best substrate biasing technique is implemented. The proposed design is better in terms of power, delay and power delay product in comparison to other biasing conditions.
Biographie de l'auteur
B.E., M.Tech. (VLSI Design). Currently working as an Assistant Professor in Faculty of Engineering and Technology, MITS, Lakshmangarh, Sikar, Rajasthan, India.
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High Performance Domino Logic Circuits in Low Power VLSI Design
Edité par
LAP LAMBERT Academic Publishing, 2012
ISBN 10 : 3659000302
ISBN 13 : 9783659000300
Neuf
Couverture souple
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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Nehra SumanB.E., M.Tech. (VLSI Design). Currently working as an Assistant Professor in Faculty of Engineering and Technology, MITS, Lakshmangarh, Sikar, Rajasthan, India.The advancement of CMOS technologies paved the road for a g. N° de réf. du vendeur 5123921
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High Performance Domino Logic Circuits in Low Power VLSI Design : A Novel Approach
Edité par
LAP LAMBERT Academic Publishing, 2012
ISBN 10 : 3659000302
ISBN 13 : 9783659000300
Neuf
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Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
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Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The advancement of CMOS technologies paved the road for a growing market of mobile and portable electronic devices. This growth is driven by the continual integration of complex analog and digital building blocks on a single chip, so silicon area and power consumption are the two most valued aspects of the design. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this dissertation, 2:1 multiplexer and 1:2 decoder is proposed. The proposed 2:1 multiplexer and 1:2 decoder design based on proposed high performance domino logic circuit are tested in 45nm and 65nm technologies to prove its technology independence. Design is also experimented under various substrate-biasing schemes and then the best substrate biasing technique is implemented. The proposed design is better in terms of power, delay and power delay product in comparison to other biasing conditions. N° de réf. du vendeur 9783659000300
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High Performance Domino Logic Circuits in Low Power VLSI Design
Edité par
LAP LAMBERT Academic Publishing Apr 2012, 2012
ISBN 10 : 3659000302
ISBN 13 : 9783659000300
Neuf
Taschenbuch
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The advancement of CMOS technologies paved the road for a growing market of mobile and portable electronic devices. This growth is driven by the continual integration of complex analog and digital building blocks on a single chip, so silicon area and power consumption are the two most valued aspects of the design. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this dissertation, 2:1 multiplexer and 1:2 decoder is proposed. The proposed 2:1 multiplexer and 1:2 decoder design based on proposed high performance domino logic circuit are tested in 45nm and 65nm technologies to prove its technology independence. Design is also experimented under various substrate-biasing schemes and then the best substrate biasing technique is implemented. The proposed design is better in terms of power, delay and power delay product in comparison to other biasing conditions. 68 pp. Englisch. N° de réf. du vendeur 9783659000300
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High Performance Domino Logic Circuits in Low Power VLSI Design
Edité par
LAP LAMBERT Academic Publishing Apr 2012, 2012
ISBN 10 : 3659000302
ISBN 13 : 9783659000300
Neuf
Taschenbuch
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
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Taschenbuch. Etat : Neu. Neuware -The advancement of CMOS technologies paved the road for a growing market of mobile and portable electronic devices. This growth is driven by the continual integration of complex analog and digital building blocks on a single chip, so silicon area and power consumption are the two most valued aspects of the design. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this dissertation, 2:1 multiplexer and 1:2 decoder is proposed. The proposed 2:1 multiplexer and 1:2 decoder design based on proposed high performance domino logic circuit are tested in 45nm and 65nm technologies to prove its technology independence. Design is also experimented under various substrate-biasing schemes and then the best substrate biasing technique is implemented. The proposed design is better in terms of power, delay and power delay product in comparison to other biasing conditions.Books on Demand GmbH, Überseering 33, 22297 Hamburg 68 pp. Englisch. N° de réf. du vendeur 9783659000300
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