Energy Recovery Clocking Scheme to Achieve Ultra Low-Power: Resonant Energy Recovery Clocking Scheme - Couverture souple

Joshi, Vinod Kumar

 
9783659132711: Energy Recovery Clocking Scheme to Achieve Ultra Low-Power: Resonant Energy Recovery Clocking Scheme
Couverture souple
ISBN 10 : 3659132713 ISBN 13 : 9783659132711
Editeur : LAP LAMBERT Academic Publishing, 2012

Synopsis

As the scale of integration improves and technology shrinks, the more number of transistors are being packed into a chip that increases the density of the chip. This leads to the steady growth in the operating frequency and possesing capacity per chip, resulting in increased power dissipation. In modern VLSI systems, the clock is the most important signal because it controls the rate of data processing and communication. It provides a structured framework for dealing with high-complexity digital systems. Various survey and current research indicates that clock network consumes a large part of the total chip power. It is even much more than that of the ordinary logic used in the design. This book indicates the four novel low power flip-flops collectively called novel energy recovery flip-flops to reduce the power dissipation in a clock network. The energy recovery clocked flip-flops enable energy recovery from the H-tree based clock network, resulting in significant energy saving. The energy recovery flip-flops operate with a single phase sinusoidal clock generated by an efficient power clock generator.

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Présentation de l'éditeur

As the scale of integration improves and technology shrinks, the more number of transistors are being packed into a chip that increases the density of the chip. This leads to the steady growth in the operating frequency and possesing capacity per chip, resulting in increased power dissipation. In modern VLSI systems, the clock is the most important signal because it controls the rate of data processing and communication. It provides a structured framework for dealing with high-complexity digital systems. Various survey and current research indicates that clock network consumes a large part of the total chip power. It is even much more than that of the ordinary logic used in the design. This book indicates the four novel low power flip-flops collectively called novel energy recovery flip-flops to reduce the power dissipation in a clock network. The energy recovery clocked flip-flops enable energy recovery from the H-tree based clock network, resulting in significant energy saving. The energy recovery flip-flops operate with a single phase sinusoidal clock generated by an efficient power clock generator.

Biographie de l'auteur

Dr. Vinod Kumar Joshi is Assistant Professor at the Dept. of Electronics and Communication at MIT, Manipal University, India. He received his M. Tech. degree from VIT University, Vellore, India and Ph. D. degree from Kumaun University, Nainital, India. His latest research focused on low power VLSI design.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2012
Langue
anglais
ISBN 10 
3659132713
ISBN 13 
9783659132711
Reliure
Broché
Nombre de pages
100
Coordonnées du fabricant
non disponible
Personne responsable
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